Datasheet

Table 2. Supported Platforms and Ports
Supported Platforms Port
Nexys
™
3 Platform (Spartan
®
-6)
JB1
ZedBoard
™
platform (Zynq
®
-7020)
JA1
The Campbell subsystem is best suited for a high-accuracy 4–20mA current loop or a 0.2V to 4.096V input
voltage analog-to-digital data acquisition system. The hardware design provides both isolated power (MAX256)
and isolated data (MAX14850).
The MAX44250 op amp (U1) input circuit buffers a 4–20mA current-loop sense voltage on a 200Ω load resistor
(with JU2 closed) or a 0.2V to 4.096V (with JU2 open) voltage signal.
The MAX11100 (U2) is a 16-bit, successive-approximation register (SAR) ADC with AutoShutdown
™
and fast
1.1µs wake-up features. The ADC's reference input is driven by the MAX6126 ultra-high-precision 4.096V
voltage reference (U3) with 0.02% initial accuracy and a 3ppm/°C maximum temperature coefficient (tempco).
The MAX256 (U4) provides an isolated, functional insulation class power solution that accepts 3.3V and
converts it to 12V using an off-the-shelf TGM-H281NF Halo
®
transformer with a 1:2.6 primary to secondary
turns ratio plus an external on-board voltage-doubler circuit. Post-regulation is accomplished using the
MAX1659 low dropout (LDO) regulators (U5 for a 12V output, U6 for an analog 5V output, and U8 for a digital
5V output). Data isolation is accomplished using the MAX14850 (U5) digital data isolator. The combined power
and data isolation achieved is 600V
RMS
.
To use the on-board isolated power supplies, move the shunt on jumper JU3 to the 1–2 position and move the
shunt on jumper JU4 to the 2–3 position. If power isolation is not required, an external 12V DC power supply
can be used. Move the shunt on jumper JU3 to the 2–3 position and move the shunt on jumper JU4 to the 1–2
position. Connect the ground terminal of the external power supply to the GND2 connector. Connect the 12V
DC power supply to the EXT_V connector. See Table 1 for the jumper settings and the input current
requirements.
Detailed Description of Firmware for Nexys 3 Platform
The Campbell firmware design was initially released for the Nexys 3 development kit and targeted a
MicroBlaze
™
soft core microcontroller placed inside a Xilinx
®
Spartan-6 FPGA. Support for additional platforms
may be added periodically under Firmware Files in the All Design Files section. The currently supported
platforms and ports are shown in Table 2.
The firmware is a working example of how to interface to the hardware, collect samples, and save them to
memory. The simple process flow is shown in Figure 2a. The firmware is written in C using the Xilinx SDK tool,
which is based on the Eclipse
™
open source standard. Custom Campbell-specific design functions were
created utilizing the standard Xilinx XSpi core version 3.03a. The SPI clock frequency is set to 3.125MHz.
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