Datasheet

MX7534/MX7535
Microprocessor-Compatible,
14-Bit DACs
______________________________________________________________________________________ 15
ADDRESS
DECODE
CS
WR
D0–D7
A0 A1
MX7534*
*SOME CIRCUITRY OMITTED FOR CLARITY
ADDRESS BUS
A0–A15
MC6809
D0–D7
Q
E
R/W
DATA BUS
Figure 13a. MX7534—MC6809 Interface Circuit
ADDRESS
DECODE
ADDRESS BUS
CS
WR
D0–D7
A0 A1
MX7534*
*SOME CIRCUITRY OMITTED FOR CLARITY
ADDRESS BUS
A0–A15
6502
D0–D7
R/W
2
DATA BUS
Figure 13b. MX7534—6502 Interface
EN
QUAD LATCH
EN
QUAD LATCH
EN
QUAD LATCH
ADDRESS
DECODE
MICRO-
PROCESSOR
SYSTEM
A0–A15
WR
A0
A1
CS
A0 A1
D0–D7
D0–D7
MX7534*
*SOME CIRCUITRY OMITTED FOR CLARITY
WR
Figure 14a. MX7534—Interface Circuit Using Latches to
Minimize Digital Feedthrough
ADDRESS
DECODE
EN
16-BIT
LATCH
CSMSB
WR
D0–D13
MX7535*
*SOME CIRCUITRY OMITTED FOR CLARITY
CSLSB
LDAC
A0–A15
MICRO-
PROCESSOR
SYSTEM
D0–D15
WR
Figure 14b. MX7535—Interface Circuit Using Latches to
Minimize Digital Feedthrough
ADDRESS
DECODE
ADDRESS BUS
DATA BUS
MREQ
Z80
A0–A15
LDAC
CSMSB
CSLSB
WR
D0–D7
D8–D13
D8–D7
MX7535*
*SOME CIRCUITRY OMITTED FOR CLARITY
WR
Figure 12a. MX7535—Z80 Interface
ADDRESS
DECODE
CS
WR
D0–D7
A0 A1
MX7534*
*SOME CIRCUITRY OMITTED FOR CLARITY
ADDRESS BUS
A0–A15
Z80
D0–D7
WR
MREQ
DATA BUS
Figure 12b. MX7534—Z80 Interface