Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External PDIP 16

General Description

The MX7705 low-power, 2-channel, serial-output ana-

log-to-digital converter (ADC) includes a sigma-delta

modulator with a digital filter to achieve 16-bit resolution

with no missing codes. This ADC is pin compatible and

software compatible with the AD7705. The MX7705 fea-

tures an on-chip input buffer and programmable-gain

amplifier (PGA). The device offers an SPI™-/QSPI™-/

MICROWIRE™-compatible serial interface.

The MX7705 operates from a single 2.7V to 5.25V supply.

The operating supply current is 320µA (typ) with a 3V

supply. Power-down mode reduces the supply current to

2µA (typ).

Self-calibration and system calibration allow the MX7705

to correct for gain and offset errors. Excellent DC perfor-

mance (±0.003% FSR INL) and low noise (650nV) make

the MX7705 ideal for measuring low-frequency signals

with a wide dynamic range. The device accepts fully dif-

ferential bipolar/unipolar inputs. An internal input buffer

allows for input signals with high source impedances. An

on-chip digital filter, with a programmable cutoff and out-

put data rate, processes the output of the sigma-delta

modulator. The first notch frequency of the digital filter is

chosen to provide 150dB rejection of common-mode

50Hz or 60Hz noise and 98dB rejection of normal-mode

50Hz or 60Hz noise. A PGA and digital filtering allow sig-

nals to be directly acquired with little or no signal-condi-

tioning requirements.

The MX7705 is available in a 16-pin TSSOP package.

Applications

Industrial Instruments

Weigh Scales

Strain-Gauge Measurements

Loop-Powered Systems

Flow and Gas Meters

Medical Instrumentation

Pressure Transducers

Thermocouple Measurements

RTD Measurements

Features

o Pin Compatible and Software Compatible with the

AD7705

o 16-Bit Sigma-Delta ADC

o Two Fully Differential Input Channels

o 0.003% Integral Nonlinearity with No Missing Codes

o Interface with Schmitt Triggers on Inputs

o Internal Analog Input Buffers

o PGA from 1 to 128

o Single (2.7V to 3.6V) or (4.75V to 5.25V) Supply

o Low Power

1mW (max), 3V Supply

2μA (typ) Power-Down Current

o SPI-/QSPI-/MICROWIRE-Compatible 3-Wire Serial

Interface

MX7705

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

________________________________________________________________

Maxim Integrated Products

SCLK

GND

DIN

DOUT

DRDY

AIN2-

REF-

REF+

TOP VIEW

MX7705

TSSOP

CLKIN

CLKOUT

AIN2+

RESET

AIN1+

AIN1-

Pin Configuration

Ordering Information

19-3051; Rev 4; 2/10

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN- PACKAGE

MX7705EUE+ -40°C to +85°C 16 TSSOP

SPI/QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

Denotes a lead(Pb)-free/RoHS-compliant package.

Summary of content (33 pages)

PAGE 1
9-3051; Rev 4; 2/10 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC Features The MX7705 low-power, 2-channel, serial-output analog-to-digital converter (ADC) includes a sigma-delta modulator with a digital filter to achieve 16-bit resolution with no missing codes. This ADC is pin compatible and software compatible with the AD7705. The MX7705 features an on-chip input buffer and programmable-gain amplifier (PGA). The device offers an SPI™-/QSPI™-/ MICROWIRE™-compatible serial interface.
PAGE 2
MX7705 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V All Other Pins to GND.................................-0.3V to (VDD + 0.3V) Maximum Current Input into Any Pin ..................................50mA Continuous Power Dissipation (TA = +70°C) TSSOP (derate 9.4mW/°C above +70°C) ....................755mW Operating Temperature Range ..........................
PAGE 3
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC (VDD = 3V or 5V, GND = 0, VREF+ = 1.225V for VDD = 3V and VREF+ = 2.5V for VDD = 5V, VREF- = GND, external fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1µF, CREF- to GND = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.
PAGE 4
MX7705 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V or 5V, GND = 0, VREF+ = 1.225V for VDD = 3V and VREF+ = 2.5V for VDD = 5V, VREF- = GND, external fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1µF, CREF- to GND = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CLKIN INPUT CLKIN Input High Voltage VCLKINH CLKIN Input Low Voltage VCLKINL CLKIN Input Current VDD = 4.75V to 5.25V 3.
PAGE 5
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC (VDD = 3V or 5V, GND = 0, VREF+ = 1.225V for VDD = 3V and VREF+ = 2.5V for VDD = 5V, VREF- = GND, external fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1µF, CREF- to GND = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.25 V POWER REQUIREMENTS Power-Supply Voltage VDD 2.70 Unbuffered fCLKIN =1MHz, gain =1 to 128 Buffered, fCLKIN =1MHz, gain =1 to 128 Unbuffered, fCLKIN = 2.
PAGE 6
MX7705 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC TIMING CHARACTERISTICS (VDD = 3V or 5V, GND = 0, VREF+ = 1.225V for VDD = 3V and VREF+ = 2.5V for VDD = 5V, VREF- = GND, external fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1µF, CREF- to GND = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.
PAGE 7
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC (VDD = 3V or 5V, GND = 0, VREF+ = 1.225V for VDD = 3V and VREF+ = 2.5V for VDD = 5V, VREF- = GND, external fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1µF, CREF- to GND = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.) (Note 16) (Figures 8, 9) Note 1: These errors are in the order of the conversion noise shown in Tables 1 and 3. This applies after calibration at the given temperature.
PAGE 8
MX7705 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC Table 1. Output RMS Noise vs. Gain and Output Data Rate (VDD = 5V) FILTER FIRST NOTCH AND OUTPUT DATA RATE TYPICAL OUTPUT RMS NOISE (µV) -3dB FREQUENCY GAIN 1 2 4 8 16 32 64 128 BUFFERED (fCLKIN = 1MHz) 20Hz 5.24Hz 4.44 2.28 1.29 0.79 0.70 0.70 0.64 0.63 25Hz 6.55Hz 5.11 2.79 1.55 0.92 0.81 0.80 0.73 0.74 100Hz 26.2Hz 102.35 49.59 23.04 11.78 6.32 3.63 2.25 2.24 200Hz 52.4Hz 586.93 272.83 224.79 70.78 33.
PAGE 9
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC FILTER FIRST NOTCH AND OUTPUT DATA RATE MX7705 Table 2. Peak-to-Peak Resolution vs. Gain and Output Data Rate (VDD = 5V) TYPICAL PEAK-TO-PEAK RESOLUTION (BITS) -3dB FREQUENCY GAIN 1 2 4 8 16 32 64 128 BUFFERED (fCLKIN = 1MHz) 20Hz 5.24Hz 16 16 16 16 16 15 14 13 25Hz 6.55Hz 16 16 16 16 16 15 14 13 100Hz 26.2Hz 12 12 12 12 12 12 12 11 200Hz 52.4Hz 10 10 10 10 10 10 10 9 UNBUFFERED (fCLKIN = 1MHz) 20Hz 5.
PAGE 10
MX7705 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC Table 3. Output RMS Noise vs. Gain and Output Data Rate (VDD = 3V) FILTER FIRST NOTCH AND OUTPUT DATA RATE TYPICAL OUTPUT RMS NOISE (µV) -3dB FREQUENCY GAIN 1 2 4 8 16 32 64 128 3.52 1.84 2.19 0.73 0.66 0.62 0.62 0.62 0.69 BUFFERED (fCLKIN = 1MHz) 20Hz 5.24Hz 25Hz 6.55Hz 4.24 2.23 1.19 0.84 0.74 0.69 0.69 100Hz 26.2Hz 50.36 25.12 12.06 6.04 3.38 2.23 1.70 1.69 200Hz 52.4Hz 268.02 175.98 65.77 34.89 16.73 8.
PAGE 11
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC FILTER FIRST NOTCH AND OUTPUT DATA RATE MX7705 Table 4. Peak-to-Peak Resolution vs. Gain and Output Data Rate (VDD = 3V) TYPICAL PEAK-TO-PEAK RESOLUTION (BITS) -3dB FREQUENCY GAIN 1 2 4 8 16 32 64 128 BUFFERED (fCLKIN = 1MHz) 20Hz 5.24Hz 16 16 16 16 15 14 13 12 25Hz 6.55Hz 16 16 16 16 15 14 13 12 100Hz 26.2Hz 12 12 12 12 12 12 12 11 200Hz 52.4Hz 10 10 10 10 10 10 10 9 20Hz 5.
PAGE 12
Typical Operating Characteristics (continued) (VDD = 3V or 5V, VREF+ = 1.225V for VDD = 3V, VREF+ = 2.5V for VDD = 5V, VREF- = GND, TA = +25°C, unless otherwise noted.) 0 -0.001 -0.002 0.001 0 VDD = 3V 4.85 4.95 5.05 5.15 5.25 -0.0015 -40 -15 SUPPLY VOLTAGE (V) 10 35 60 2.70 85 2.85 0.004 0.003 GAIN ERROR (%FSR) 0.001 0 -0.001 MX7705 toc08 0.005 MX7705 toc07 VDD = 5V 3.15 GAIN ERROR vs. TEMPERATURE GAIN ERROR vs. SUPPLY VOLTAGE (5V) 0.002 3.00 VDD = 3V 0.002 0.001 0 -0.001 -0.
PAGE 13
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC 0.5 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) MX7705 toc09 VDD = 3V A B 0.4 C D 0.3 0.65 A MX7705 toc10 SUPPLY CURRENT vs. SUPPLY VOLTAGE (5V) SUPPLY CURRENT vs. SUPPLY VOLTAGE (3V) 0.6 VDD = 5V B 0.55 0.45 C D 0.35 E E 0.25 0.2 2.70 2.85 3.00 3.15 3.30 3.45 4.75 3.60 4.85 4.95 5.05 5.15 5.25 SUPPLY VOLTAGE (V) A: BUFFERED MODE B: BUFFERED MODE C: BUFFERED MODE fCLKIN = 2.4576MHz, fCLKIN = 2.
PAGE 14
Typical Operating Characteristics (continued) (VDD = 3V or 5V, VREF+ = 1.225V for VDD = 3V, VREF+ = 2.5V for VDD = 5V, VREF- = GND, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. fCLKIN (3V) 0.5 0.4 C D 0.3 VDD = 5V MX7705 toc14 B SUPPLY CURRENT (mA) B A 0.55 0.45 C D 0.35 E E 0.2 0.25 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.
PAGE 15
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC 60 40 20 0 200 VDD = 5V 180 160 140 120 300 250 VDD = 5V 200 150 100 100 2.70 2.85 3.00 3.15 3.30 SUPPLY VOLTAGE (V) 3.45 3.60 MX7705 toc19 80 POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE MX7705 toc18 VDD = 3V POWER-DOWN SUPPLY CURRENT (nA) MX7705 toc17 POWER-DOWN SUPPLY CURRENT (nA) 100 POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE (5V) POWER-DOWN SUPPLY CURRENT (μA) POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE (3V) VDD = 3V 50 0 4.
PAGE 16
-Bit, Low-Power, 2-Channel, Sigma-Delta ADC MX7705 Pin Description 16 PIN NAME FUNCTION 1 SCLK Serial Clock Input. Apply an external serial clock to transfer data to and from the device at data rates of up to 5MHz. 2 CLKIN Clock Input. Connect a crystal/resonator between CLKIN and CLKOUT, or drive CLKIN externally with a CMOS-compatible clock source with CLKOUT left unconnected. 3 CLKOUT 4 CS 5 RESET Active-Low Reset Input. Drive RESET low to reset the MX7705 to power-on reset status.
PAGE 17
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC DIVIDER CLOCK GENERATOR CLKIN CLKOUT MX7705 BUFFER AIN1+ AIN1AIN2+ SWITCHING NETWORK S1 S2 PGA 2ND-ORDER SIGMA-DELTA MODULATOR DIGITAL FILTER VDD GND AIN2BUFFER S1 AND S2 ARE OPEN IN BUFFERED MODE AND CLOSED IN UNBUFFERED MODE REF+ SERIAL INTERFACE, REGISTERS, AND CONTROL CS SCLK DIN DOUT DRDY RESET REF- Detailed Description The MX7705 low-power, 2-channel, serial-output ADC uses a sigma-delta modulator with a digital filter to achieve 16-bit res
PAGE 18
To minimize gain errors in unbuffered mode, select a source impedance less than the maximum values shown in Figures 2 and 3. These are the maximum external resistance/capacitance combinations allowed before gain errors greater than 1 LSB are introduced in unbuffered mode. Enable the internal input buffer for a high source impedance. This isolates the inputs from the sampling capacitor and reduces the sampling-related gain error.
PAGE 19
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC MX7705 Table 5. Input Sampling Capacitor vs. Gain VREF / GAIN INPUT SAMPLING CAPACITOR (CSAMP) (pF) 3.75 15 8–128 30 Increasing the gain increases the resolution of the ADC (LSB size decreases), but reduces the differential input voltage range.
PAGE 20
Modulator The MX7705 performs analog-to-digital conversions using a single-bit, 2nd-order, switched-capacitor, sigma-delta modulator. The sigma-delta modulation converts the input signal into a digital pulse train whose average duty cycle represents the digitized signal information. A single comparator within the modulator quantizes the input signal at a much higher sample rate than the bandwidth of the input.
PAGE 21
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC Serial-Digital Interface The MX7705 interface is fully compatible with SPI-, QSPI-, and MICROWIRE-standard serial interfaces. The serial interface provides access to seven on-chip registers. The registers are 8, 16, and 24 bits in size. Drive CS low to transfer data in and out of the MX7705. Clock in data at DIN on the rising edge of SCLK. Data at DOUT changes on the falling edge of SCLK and is valid on the rising edge of SCLK.
PAGE 22
MX7705 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC DIN RS2 RS1 RS0 COMMUNICATIONS REGISTER SETUP REGISTER (8 BITS) CLOCK REGISTER (8 BITS) REGISTER SELECT DECODER DATA REGISTER (16 BITS) DOUT TEST REGISTER (8 BITS)* OFFSET REGISTER (24 BITS) GAIN REGISTER (24 BITS) *THE TEST REGISTER IS USED FOR FACTORY TESTING ONLY. Figure 10. Register Summary Communications Register The byte-wide communications register is bidirectional so it can be written and read.
PAGE 23
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC FIRST BIT (MSB) FUNCTION (LSB) COMMUNICATION START/DATA READY Name REGISTER SELECT READ/WRITE SELECT POWER-DOWN MODE CHANNEL SELECT 0/DRDY RS2 RS1 RS0 R/W PD CH1 CH0 0 0 0 0 0 0 0 0 Defaults Table 7.
PAGE 24
MX7705 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC Table 10. Operating-Mode Selection MD1 MD0 0 0 Normal Mode. Use this mode to perform normal conversions on the selected analog input channel. 1 Self-Calibration Mode. This mode performs self-calibration on the selected channel determined from CH0 and CH1 selection bits in the communications register (Table 6). Upon completion of self-calibration, the device returns to normal mode with MD0, MD1 returning to 0, 0.
PAGE 25
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC Write to the calibration registers in normal mode only. After writing to the calibration registers, the devices implement the new offset and gain-register calibration coefficients at the beginning of a new acquisition. To ensure the results are valid, discard the first conversion result after writing to the calibration registers.
PAGE 26
MX7705 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC Reset Drive RESET low to reset the MX7705 to power-on reset status. DRDY goes high and all communication to the MX7705 is ignored while RESET is low. Upon releasing RESET, the device must be reconfigured to begin a conversion. The device returns to waiting for a write to the communication register after a reset has been performed. Perform a calibration sequence following a reset for accurate conversions.
PAGE 27
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC MX7705 POWER-ON RESET INITIALIZE μC/μP SERIAL PORT WRITE TO THE COMMUNICATIONS REGISTER. SELECT CHANNEL 1 AND SET NEXT OPERATION AS A WRITE TO THE CLOCK REGISTER. (0x20) WRITE TO THE CLOCK REGISTER. ENABLE EXTERNAL OSCILLATOR. SELECT OUTPUT UPDATE RATE OF 60Hz. (0xA5) WRITE TO THE COMMUNICATIONS REGISTER. SELECT CHANNEL 1 AND SET NEXT OPERATION AS A WRITE TO THE SETUP REGISTER. (0x10) WRITE TO THE SETUP REGISTER.
PAGE 28
MX7705 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC Using FSYNC When FSYNC = 1, the digital filter and analog modulator are in a reset state, inhibiting normal operation. Set FSYNC = 0 to begin calibration or conversion. When configured for normal operation (MD0 and MD1 set to 0), DRDY goes low 3 x 1/output data rate after FSYNC goes low to indicate that the new conversion result is ready to be read from the data register. DRDY returns high when a read operation on the data register is complete.
PAGE 29
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC The DRDY output goes high at the start of calibration and falls low when the calibration is complete and the next conversion result is valid in the data register. The total time for self-calibration and one conversion (time until DRDY goes low) is 9 x 1/output data rate.
PAGE 30
MX7705 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC Applications Information VDD Applications Examples Strain-Gauge Measurement Connect the differential inputs of the MX7705 to the bridge network of the strain gauge. In Figure 12, the analog positive supply voltage powers the bridge network and the MX7705, along with the reference voltage in a ratiometric configuration. The on-chip PGA allows the MX7705 to handle an analog input voltage range as low as 20mV to full scale.
PAGE 31
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC ISO 3V/5V Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line is either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. INL for the MX7705 is measured using the endpoint method. This is the more conservative method.
PAGE 32
MX7705 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC Package Information Chip Information TRANSISTOR COUNT: 42,000 PROCESS: BiCMOS 32 For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
PAGE 33
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC REVISION NUMBER REVISION DATE 3 6/09 Corrected values in Reference section 18 4 2/10 Removed unreleased package options 1, 2, 32 DESCRIPTION PAGES CHANGED Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.