Datasheet

MX7705
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
6 _______________________________________________________________________________________
TIMING CHARACTERISTICS
(V
DD
= 3V or 5V, GND = 0, V
REF+
= 1.225V for V
DD
= 3V and V
REF+
= 2.5V for V
DD
= 5V, V
REF-
= GND, external f
CLKIN
=
2.4576MHz, CLKDIV bit = 0, C
REF+
to GND = 0.1µF, C
REF
- to GND = 0.1µF, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 16)
(Figures 8, 9)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DRDY High Time
500 /
f
CLKIN
s
Reset Pulse-Width Low 100 ns
DRDY Fall to CS Fall Setup Time t
1
0ns
CS Fall to SCLK Rise Setup Time t
2
120 ns
V
DD
= 4.75V to 5.25V 0 80
SCLK Fall to DOUT Valid Delay t
3
V
DD
= 2.7V to 3.6V 0 100
ns
SCLK Pulse-Width High t
4
100 ns
SCLK Pulse-Width Low t
5
100 ns
CS Rise to SCLK Rise Hold Time t
6
0ns
V
DD
= 4.75V to 5.25V 60
Bus Relinquish Time After SCLK
Rising Edge
t
7
V
DD
= 2.7V to 3.6V 100
ns
SCLK Fall to DRDY Rise Delay t
8
100 ns
DIN to SCLK Setup Time t
9
30 ns
DIN to SCLK Hold Time t
10
20 ns