Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide Rev 0; 2/14 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2014 Maxim Integrated Products, Inc.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide Table of Contents 1. Required Equipment ................................................................................................. 3 2. Overview ................................................................................................................... 3 3. Included Files ........................................................................................................... 5 4. Procedure ..........................................
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide 1. Required Equipment • • • • • PC with Windows® OS with Xilinx® ISE®/SDK version 14.2 or later and two USB ports (Refer to Xilinx AR# 51895 if you installed ISE WebPackTM design software on your PC.) License for Xilinx EDK/SDK version 14.2 or later (free WebPack license is OK) Petaluma (MAXREFDES30#) board ZedBoardTM development kit Industrial sensor or signal source 2.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide Figure 1.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide 3. Included Files The top level of the hardware design is a Xilinx PlanAhead™ Project (.PRR) for Xilinx PlanAhead version 14.2. The Verilog-based arm_system_stub.v module provides FPGA/board net connectivity, and instantiates the wrapper that carries both the Zynq® Processing System and AXI_MAX11046 custom IP core that interface to the FMC connector.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide 4. Procedure 1. Install a 2-pin header on the J18 connector on the ZedBoard if the 3V3 header is missing. 2. Remove any shunt on 1V8 and 2V5 headers, and install a shunt on the 3V3 header. 3. Connect the Petaluma board to the J1 FMC connector of the ZedBoard as shown in Figure 1. 4. Power up the ZedBoard by sliding the SW8 switch on the ZedBoard to the ON position. 5. Download the latest RD30V01_00.ZIP file at www.maximintegrated.com/Petaluma.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide 7. Open the Xilinx Software Development Kit (SDK) from the Windows Start menu. 8. SDK will prompt for a workspace directory, which is the location where the software project is located. For this example, it is: C:\designs\maxim\RD30V01_00\RD6_ZED_V01_00\Design_Files\top.sdk\SDK\ SDK_Export Click OK and SDK will open. The Xilinx SDK is based on an Eclipse™-based IDE, so it will be a familiar flow for many software developers.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide 9. Review the SDK IDE. The Project Explorer in the upper left tab should have three components as shown in the image below. If all three subfolders are present, you can skip the next step.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide 10. If the Project Explorer does not contain these three subfolders, launch the File | Import menu, expand the General folder, and select Existing Projects into Workspace. Click Next. Set the root directory to: C:\designs\maxim\RD30V01_00\RD30_ZED_V01_00\Design_Files\top.sdk\SDK\ SDK_Export and the missing projects should appear in SDK Project Explorer with their checkboxes checked. Click Finish to import the projects.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide 11. To download the bitstream (.BIT) file to the board, click on the Program FPGA icon (which looks like a green chain of devices). The Program FPGA dialog box appears. From here, an FPGA bitstream (.BIT) file is selected. Be sure to select the .BIT file by using the paths below. Bitstream: C:\designs\maxim\RD30V01_00\RD30_ZED_V01_00\Design_Files\top.sdk\ SDK\SDK_Export\arm_system_hw_platform Press Program.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide 12. Set up the terminal program to run on the PC using the following steps. Before loading the executable firmware file on the FPGA, the terminal program on the PC should be running. The example firmware running on the FPGA communicates with the PC via a USB port set up to emulate a serial port (UART). To establish this communication link, the PC must be configured with the appropriate Windows drivers.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide 13. Use the Xilinx SDK to download and run the executable ELF (.ELF) file on the ARM Cortex-A9 processor using the following steps. Right-click the mouse while the MAXREFDES30 C project is selected, choose the Run As menu, and then Run Configurations… menu as shown below.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide Next, double-click the mouse on the Xilinx C/C++ ELF menu.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide Next, press the Search Project button.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide Double-click on the MAXREFDES30.elf binary.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide Verify the application is selected on the Main tab.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide On the Device Initialization tab, click Browse… button to select the right initialization TCL file and press the Run button. Once the Debug/MAXREFDES30 configuration is set up once, you just need to press the Run button if you ever want to run the program again.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide At this point, the application is running on the Cortex-A9 and the terminal program should show the menu below. Make the desired selections by pressing the appropriate keys on the keyboard. For example, to select continuous sampling, press 0.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide 5. Code Documentation Code documentation can be found at: C:\...\RD30V01_00\RD30_ZED_V01_00\Code_Documentation\ To view the code documentation in HTML format with a browser, open the MainPage.html file. To view the code documentation in .PDF format with a PDF reader, open the MAXREFDES30_Code_Documentation.pdf file.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide 6. Appendix A: Project Structure and Key Filenames Top level folder contains: • Numerous source and intermediate files (PlanAhead generated) • top.ppr = main Xilinx PlanAhead project file. • top.* = the Xilinx PlanAhead top level project folders SDK Export Folder • \MAXREFDESX = C Project Folder \src\MAXREFDESX.c = Main example program \src\maximDeviceSpecificUtilities.c = driver functions \src\menu.c = menu functions \src\utilities.
Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide 8.
