User's Manual

Maxon SM5102Radio
3 DETAILED FUNCTIONAL DESCRIPTION
3.1 VHF Transmit
1. Buffer
2. Power AMP
3. Low Pass Filter
4. Antenna Switch
5. A.P.C Circuits
Buffer
VCO output level is 0dBm and amplified to +17dBm (UHF)/(VHF). The buffer consists of Q2, 12,13 for isolation and
gain.
Power AMP
The P.A Module(Q28) consists of 3-stage(Q18,Q39,Q28) amplifier and amplifies the TX signal from +37dBm to
(+46~47)dBm. The input and the output terminal of the P.A Module are matcued 50 OHM.
Low Pass Filter
L21,25,L22,L27,C103,168,296,100,65,297,99 are Chebyshev low pass filter. Unwanted harmonic are reduced by -65
dBc.
Antenna Switch
When transmitting, the diodes D15 and D2 are forward biased enabling the RF signal passage to the antenna. D15,D2
is shorted to ground inhibiting the RF signal to front-end. In receive the diodes D1 and D15/2 are reversed biased
passing the signal from the antenna through L24 and C111 to the front-end without signal loss.
Automatic Power Control Circuit
The APC circuit consists of the R109, variable resistor RV1,5, U11, and Transistor Q34, Q37, and Q14,Q15,Q16. The
supply current is monitored by difference voltage on R249 which is through for it. If the current is varied by RF power
output or other reasons, it produces some bias voltage by U11 and Q34. The differential signal at the output of U11 is
passed to Q14 and Q15that produces a constant power output to the antenna. RV5 is used to adjust the RF power level.
12.8 MHz TCXO
The TCXO contains the 2-stage thermistor network compensation and crystal oscillator and modulation ports.
Compensation is +/-2.5 PPM or less from -30c to +60c.
PLL IC Dual Modules Prescaler
Input frequency of 12.8 MHz to U1 MB15E03SL pin 16 is divided to 6.25 KHz or 5 KHz by the reference counter,
and then supplied to comparator. RF signal input from VCO is divided to 1/64 at prescaler in U1, Divided by A and N
counter in IU1 to determine frequency steps, and then supplied to the comparator. PLL comparison frequency is
6.25/5KHz so that minimum programmable frequency step is 5/6.25 KHz. A and N counter is programmed to obtain the
desired frequency by serial data in CPU. In comparator, the phase difference between reference and VCO signal is
compared. When the phase of reference frequency is leading , Fv is output, but when VCO frequency is leading, Fr is
the output. When Fv=Fr, phase detector out is very small 0v pulse. 64/65 modulus prescaler is comprised in U1.