__________________________________________________________________________________________________ Technical Specification ATA Flash Memory Card Full Size PCMCIA Card Version 7.
Introduction : The FCA Series ATA Flash Card is a flash technology based, ATA interface, Type II PC Card using most advanced Flash ATA controller chips interfacing with Samsung or Hitachi NAND-based flash memory devices. The PC card operates from a single 3.5/5-Volt power supply and comes in capacity form 32MB up to 2048 MB unformatted.
Features: • PC Card compliant ◊ Fully compatible with PC Card standard and PC Card ATA ◊ Backward compatible with PCMCIA 2.
Product Specifications : Dimensions: Type II card : Weight : 85.6mm(L) x 54mm(W) x 5mm(H) 50 g or 1.8 oz Storage Capacities: 32, 48, 64, 128, 256, 512, 1024, 2048 Mbytes (unformatted) System Compatibility: l Hewlett Packard 95/100/200LX l Hewlett Packard OmniGo 100 l IBM compatible Notebook PCs, Laptops, Palmtops, or Hand-held devices, etc.
Order Information FCAxxxM-13Y-02 xxxx = Y=C Y=I Y=R Capacity Standard Temp. Industrial Temp.
Physical Outline Unit: mm Surface A 54.00 ± 0.10 Surface A 5.0 (max) 85.60 ± 0.20 10.0 min 34pin Surface A 3.3 ± 0.1 1pin 1.27 ± 0.1 35pin 68pin 1.27 ± 0.1 41.
PCMCIA Interface : The PCMCIA standard, originally created to standardize memory-card to personal-computer interface, now includes I/O devices. It defines signals, voltage levels, and socket- and cardcervices that control hardware. The PC Card-ATA Mass Storage Standard combines PC card interface requirements with the industry-standard ATA specification. In addition to primary and secondary ATA addressing modes, PCMCIA specifies linear, independent I/O and linear memory-mapped modes.
Pin Assignments PCMCIA-ATA memory and I/O mode pin descriptions Pin 1 2 PCMCIA-ATA PCMCIA-ATA Memory Signal I/O Signal 1 GND GND 2 D3 D3 3 D4 D4 4 D5 D5 5 D6 D6 6 D7 D7 7 CE1# CE1# 8 A10 N.U. 9 OE# N.U. 10 N.C. N.C. 11 A9 A9 12 A8 A8 13 N.C. N.C. 14 N.C. N.C. 15 WE# N.U. 16 RDY/BSY# IREQ# 17 VCC VCC 18 N.C. N.C. 19 N.C. N.C. 20 N.C. N.C. 21 N.C. N.C. 22 A7 A7 23 A6 A6 24 A5 A5 25 A4 A4 26 A3 A3 27 A2 A2 28 A1 A1 29 A0 A0 30 D0 D0 31 D1 D1 32 D2 D2 33 WP IOIS16# 34 GND GND N.C.
Pin 1 2 PCMCIA-ATA PCMCIA-ATA Memory Signal I/O Signal 35 GND GND 36 CD1# CD1# 37 D11 D11 38 D12 D12 39 D13 D13 40 D14 D14 41 D15 D15 42 CE2# CE2# 43 N.C. N.C. 44 N.U. IORD# 45 N.U. IOWR# 46 N.C. N.C. 47 N.C. N.C. 48 N.C. N.C. 49 N.C. N.C. 50 N.C. N.C. 51 VCC VCC 52 N.C. N.C. 53 N.C. N.C. 54 N.C. N.C. 55 N.C. N.C. 56 N.U. N.U. 57 N.C. N.C. 58 RESET RESET 59 WAIT# WAIT# 60 INPACK# INPACK# 61 REG# REG# 62 Pullup Pullup 63 Pullup STSCHG# 64 D8 D8 65 D9 D9 66 D10 D10 67 CD2# CD2# 68 GND GND N.C.
GND D0-15 1,34,35,68 2-6,30-32, 37-41,64-66 7 8,10-14, 19-29, 46-50,53-56 9 Ground between the host and drive. I/O Bi-directional data bus between the host and drive. CE1# I Card Enable 1 enables even data bytes on D0-7. A0-25 I Addresses A0-10 access data and registers depending on the memory or I/O mode chosen by the host. Addresses A11-24 are not used. OE# I Output Enable reads attribute- and memory-mode data on D0-15. WE# 15 I Write Enable reads attribute- and memory-mode data on D0-15.
registers are located on even-byte attribute-plane addresses to ensure access in 8- and 16-bit system. Available card status information allows arbitration between resources that share interrupts and status of memory-only-card pins 16, 33, 62, and 63. Register Add.
SigChg The host sets/resets the Signal Changed bit to enable/disable a state-change signal from the status register. When set and the drive is configured for I/O, Chng controls pin 63 and is called the Changed Status signal. This bit should be 0 (BVD1/STSCHG# held high when configured for I/O) if no state change signal is desired. IOis8 Must be set if the host can only perform 8-bit I/O accesses. Audio Audio is not supported. PwrDn Setting PwrDn places the drive in sleep mode.
Copy # The twin-card option is not supported. Socket # The socket number is ignored. Memory and I/O Modes Decoding Memory Mode Decoding Memory mode allows hosts to access ATA registers within a 2-Kbyte contiguous memory space. The first 16 bytes contain ATA task-file registers. Offsets 400h-7FFh provide alternate ATA data register addresses. The host must decode memory addresses A11 and above to provide card-enables CE1# and CE2#. The drive decodes addresses A0-10.
Even-memory byte accesses (CE1# asserted, CE2# de-asserted, A0 = 0), at offsets between 400h and 4FFh are equivalent to offset 008h accesses. Odd-memory word accesses (CE1# asserted, CE2# de-asserted, A0 = 1), at these offsets are equivalent to offset 009h accesses. Even-memory word accesses (CE1# and CE2# asserted, A0 = don’t care), at these offsets are equivalent to offset 000h or 008h word accesses. Offsets 400h-7FFh do not correspond to actual card data-buffer addresses.
Drive/Head 006 Status 007 Command Data (duplicate) (see note 3) Read Write Read Write 008 Read Write 009 Read Write Invalid Error (duplicate) 00A-00C 00D Read Write Alternate Status Drive Control Drive Address 00E 00F Read Write Read Write H H H H H H H H H H H H H H H H H H H H H H H H H H H X X L H L H L H L H H L H L X H L H L X X H L H L L L L L L H L H L L L L L H L H X L H L H L L L H L H L L L H L L H H L L H H L L H H X L L H H L H L L H H L H H L H H L L H H L L H H L L H H H L
ATA Compliant Commands Check Power Mode Although this command is supported for backward compatibility, it has no actual function. The card will always return the Not In Standby mode code "00h" in the Sector Count register, in response to this command. Command completion status will always indicate command completed with no error.
Execute Drive Diagnostic This command performs self-diagnostics on various internal components of the card. Results of the test are reported in the Error Register. Note that the bit definitions for the Error Register do not apply in this command; rather, the value in the Error Register is a diagnostic code, defined in Table 1 below.
Format Track This command erases 32 sectors starting at the sector specified by the Cylinder, Head, and Sector Number parameters in the task file. If the sector is not valid, an IDNF (ID Not Found) ) bit is set in the Error Register and the command terminates. In CHS mode, the number of sectors to format per track will be set to the number of Current Sectors per Track in the Identify Drive data, by default 20h.
Identify Drive This command passes to the host one sector of data describing the card's parameters. See Table 2 on page 9 for a detailed description of the Identify Drive data.
Table 2. Identify Drive Information Word Data 0 848Ah 1 2 3 4 5 6 7-9 10-19 20 21 22 23-26 27-46 Note 1 0000h 0008h 4000h 0200h 0020h 0000h 0000h 0000h 2020h ...2020h 0003h 0002h 0004h ‘00001.02’ ‘ ðððð ’ 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64-127 128-159 160-255 ð ð’ ‘ððð ð’ 0001h 0000h 0200h 0000h 0200h 0000h 0001h Note 1 Note 1 Note 1 Note 1 0000h 0001h Note 1 0000h 0000h 0000h 2020h ... ... 2020h ... ...
Idle Although this command is supported for backward compatibility, it has no actual function. The card will always return good status at the completion of this command. Idle Command Issued by Host Task File Register 7 6 5 4 COMMAND DRIVE/HEAD 3 2 1 0 97h/E3h nu nu nu D nu CYLINDER HI nu CYLINDER LOW nu SECTOR START nu SECTOR COUNT Timeout Parameter. This parameter is ignored by the card.
Idle Immediate Although this command is supported for backward compatibility, it has no actual function. The card will always return good status at the completion of this command.
Initialize Drive Parameters This command allows the host to alter the number of sectors per track and the number of heads per cylinder. This enables Translation Mode which maps the flash storage using the altered parameters. On Host Reset, the default is 32 Sectors per Track and 4 Heads per Cylinder. The current values used for mapping are returned in the Identify Drive command as Number of Current Sectors per Track, and Number of Current Heads.
Read Buffer This command transfers the current contents of the first page of the data buffer (512 bytes) to the host.
Read Long (w/ and wo/ retry) This command is similar to the Read Sectors command except the contents of the Sector Count register are ignored and only one sector is read. The 512 data bytes and 4 ECC bytes are read into the buffer (with no ECC correction) and then transferred to the host.
Read Multiple This command is supported for backward compatibility. If R/W Multiple commands have been enabled by a previous valid Set Multiple command, the Read Multiple command is identical to Read Sectors operation except that several sectors are transferred as a block to the Host without intervening Host handshaking. The number of sectors to transfer as a block is referred to as the block count. The block count is established using the Set Multiple command.
Read Sectors This command transfers data from the FCA card to the Host. Data transfer starts at the sector specified by the Cylinder, Head, and Sector Number registers in the Task File, and proceeds for the number of sectors specified in the Sector Count Register.
Read Verify Sectors The Read Verify Sectors command verifies one or more sectors on the card by transferring data from the Flash media to the data buffer in the card and verifying that the ECC is correct. It is performed identically to the Read Sectors command, except that DRQ is not asserted, and no data is transferred to the host. If an uncorrectable error occurs, the read verify will be terminated at the failing sector.
Recalibrate Although this command is supported for backward compatibility, it has no actual function. The card will always return good status at the completion of this command.
Seek This command is supported for backward compatibility. Although this command has no actual function, it does perform a range check of valid track, and posts an IDNF error if the Head or Cylinder specified are out of bounds.
Set Features This command allows the host to alter the card's internal clock, choosing from three speeds to optimize performance and power. Table 3 on page 21shows the valid data which may be set in the Feature Register by the Host. All other values are invalid and will cause the ABRT (Command Aborted) bit to be set in the Error Register and the command to terminate. A feature number of 97h specifies that the FCA card’s internal clock is to be set according to the code in the Sector Count register.
Set Multiple This command is supported for backward compatibility. This command is used either to set the block count (number of sectors per block), simultaneously enabling R/W Multiple command support, or to disable support of R/W Multiple commands. Although setting, reading, and writing blocks are supported, the only valid block count is one.
Sleep Command Issued by Host Task File Register 7 6 5 4 COMMAND DRIVE/HEAD 3 2 1 0 99h/E6h nu nu nu D nu CYLINDER HI nu CYLINDER LOW nu SECTOR START nu SECTOR COUNT nu FEATURES nu Command Block specified upon completion/termination of Sleep command (99h/E6h) Task File Register 7 6 5 4 3 2 1 0 BSY DRDY DWF DSC DRQ CORR IDX ERR 0 0 0 0 STATUS 0 1 0 1 DRIVE/HEAD na na na na na CYLINDER HI na CYLINDER LOW na SECTOR na SECTOR COUNT ERROR na BBK UNC
Command Block specified upon completion/termination of Standby command (96h/E2h) Task File Register 7 6 5 4 3 2 1 0 BSY DRDY DWF DSC DRQ CORR IDX ERR 0 0 0 0 STATUS 0 1 0 1 DRIVE/HEAD na na na na na CYLINDER HI na CYLINDER LOW na SECTOR na SECTOR COUNT ERROR na BBK UNC MC IDNF MCR ABRT TK0NF AMNF 0 0 0 0 0 0 0 0 Standby Immediate Although this command is supported for backward compatibility, it has no actual function.
Command Block specified upon completion/termination of Write Buffer command (E8h) Task File Register 7 6 5 4 3 2 1 0 BSY DRDY DWF DSC DRQ CORR IDX ERR V V 0 0 STATUS 0 1 0 1 DRIVE/HEAD na na na na na CYLINDER HI na CYLINDER LOW na SECTOR na SECTOR COUNT ERROR na BBK UNC MC IDNF MCR ABRT TK0NF AMNF 0 0 0 0 0 0 0 0 Write Long (w/ and w/o retry) This command is similar to the Write Sectors (w/ retry) except the contents of the Sector Count register are ign
Write Multiple Command Issued by Host Task File Register 7 6 5 4 COMMAND 3 2 1 0 C5h DRIVE/HEAD nu L CYLINDER HI nu D H[3:0] or LBA[27:24] of the starting sector/LBA Cylinder[15:8] or LBA[23:16] of the first sector/LBA to transfer CYLINDER LOW Cylinder[7:0] or LBA[15:8] of the first sector/LBA to transfer SECTOR START Sector[7:0] or LBA[7:0] of the first sector/LBA to transfer SECTOR COUNT The number of sectors/logical blocks to transfer FEATURES nu Command Block specified upon com
Command Block specified upon completion/termination of Write Sectors command (30h/31h) Task File Register STATUS DRIVE/HEAD 7 6 5 4 3 2 1 0 BSY DRDY DWF DSC DRQ CORR IDX ERR 0 1 0 1 V V 0 V na? L na? na? CYLINDER HI H[3:0] or LBA[27:24] last good sector transferred Cylinder[15:8] or LBA[23:16] of the last good sector transferred CYLINDER LOW Cylinder[7:0] or LBA[15:8] of the last good sector transferred SECTOR Sector[7:0] or LBA[7:0] of the last good sector transferred SE
Wear Leveling Command Issued by Host Task File Register 7 6 5 4 COMMAND DRIVE/HEAD 3 2 1 0 F5h nu nu nu D nu CYLINDER HI nu CYLINDER LOW nu SECTOR START nu SECTOR COUNT nu FEATURES nu Command Block specified upon completion/termination of Wear Leveling command (F5h) Task File Register 7 6 5 4 3 2 1 0 BSY DRDY DWF DSC DRQ CORR IDX ERR V V 0 0 STATUS 0 1 0 1 DRIVE/HEAD na na na na na CYLINDER HI na CYLINDER LOW na SECTOR na SECTOR COUNT ERROR na
