Specifications

Source Organization：
：：
：
USI CVS2/RD2/NS
DOC NO.:
Original Effective Date：
：：
：
01-09-2014
AP832e / AP832i /AP822e /AP822i
Hardware
Specification
PAGE
5 OF 10
3.2 System Block Diagram for AP822e/AP822i
3.3 Design Features
3.3.1 CPU
• Freescale CPU, P1020NSE2HFB (including the security engine) must be used and
configured to operate its core at 800 MHz and DDR3 memory at 667MT/s.
3.3.2 SDRAM
• 256MB DDR3 Memory with two 64x16x8 memory devices and configured in 32 bit
wide with optional ability to increase to 512MB at a future time without PCB re-spin
required.
3.3.3 FLASH
• 32MB parallel NOR Flash in one physical device with optional ability to increase to
64MB at a future time without PCB re-spin required. The device must be Spansion
S29GL256S90TFI020 or compatible and configured in 16 bit wide..
3.3.4 Giga PHY
• The hardware design must be equipped with two Gigabit Ethernet interfaces with
shielded RJ-45 connectors, each designed with one Vitesse VSC8601 (1GbE PHY).
Only one provides PoE. The PHY must support software to control LED functions (link,
activity, etc…) and support software to disable LEDs completely.
3.3.5 CLOCK AND RESET
• A 66.66MHz oscillator will be used to provide the clock for P1020NSE2HFB
• A reset chip will be used to provide the power on reset.