Specifications

Source Organization：
：：
：
USI CVS2/RD2/NS
DOC NO.:
Original Effective Date：
：：
：
01-09-2014
AP832e / AP832i /AP822e /AP822i
Hardware
Specification
PAGE
6 OF 10
• A push button is connected to a GPIO line of the processor to restore to defaults
configurations.
3.3.6 Watchdog Timer
• The hardware design must provide a watchdog circuit, either internal to CPU or by
external logic that should generate a board-wide hardware reset if not ticked in 10 to
20 seconds, provide CPU the status indicating either power-on reset or waterdog reset,
and allow CPU reset this status back to default, power-on reset.
3.3.7 LED function
• The hardware design must support one Board Status LED in Red Green Blue tri-color
to show the status of the AP and each individual color is turned ON/OFF by software
through a GPIO.
• On each Ethernet RJ45, the hardware design should provide two integrated LEDs,
one Green and one Amber and connect Green and Amber LED to LED1 and LED2 of
VSC8601 respectively. Green LED on the left is ON when the link is established and is
Blinking when the link is up and transmitting and receiving and the right Amber LED is
OFF for half duplex or no link and is ON for full-duplex and the link is up. Both LEDs
should be directly controlled by Ethernet PHY and should allow software override to
turn both LEDs OFF either indirectly through PHY registers or directly through GPIOs.
3.3.8 GPIO define
GPIOs Description Direction Default
State
Active
GPIO_0 Detect 802.3at POE source
Input High Low
GPIO_1 Press restore to default
configuration button
Input High Low
GPIO_2 Enable USB power
Output Low High
GPIO_3 USB_FLAG status
Input High Low
GPIO_4 Power on miniPCIE P2 interface
Output High High
GPIO_5 reserved
GPIO_6 Status Blue LED
Output High Low
GPIO_7 Status Red LED
Output High Low
GPIO_8 Status Green LED
Output High Low
GPIO_9 Hard reset miniPCIE P1
Output High Low
GPIO_10 Hard reset miniPCIE P2
Output High Low
GPIO_11 Detect DC adaptor
Input High Low
GPIO_12 Hard reset Ethernet PHY1 only,
connecting to PHY1’s Hardware
Reset pin after ORing with
Power-On-Reset#, PHY1 is
connected to CPU’s SGMII1 and
not support PoE
Output High Low