Specifications

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KSZ8895MQ/RQ/FMQ

Integrated 5-Port 10/100 Managed Ethernet

Switch with MII/RMII Interface

Revision 1.7

General Description

The KSZ8895MQ/RQ/FMQ is a highly-integrated,

Layer 2 managed, five-port switch with numerous

features designed to reduce system cost. Intended for

cost-sensitive 10/100Mbps five-port switch systems

with low power consumption, on-chip termination, and

internal core power controllers, it supports

high-performance memory bandwidth and shared

memory-based switch fabric with non-blocking

configuration. Its extensive feature set includes power

management, programmable rate limit and priority

ratio, tag/port-based VLAN, packets filtering,

four-queue QoS prioritization, management interfaces,

and MIB counters. The KSZ8895 family provides

multiple CPU data interfaces to effectively address

both current and emerging fast Ethernet applications

when port 5 is configured to separate MAC5 with

SW5-MII/RMII and PHY5 with P5-MII/RMII interfaces.

The KSZ8895 family offers three configurations,

providing the flexibility to meet different requirements:

• KSZ8895MQ: Five 10/100Base-T/TX transceivers,

one SW5-MII and one P5-MII interface,

• KSZ8895RQ: Five 10/100Base-T/TX transceivers,

one SW5-RMII and one P5-RMII interface

• KSZ8895FMQ: Three 10/100Base-T/TX

transceivers on Ports 1, 2, 5 and two 100Base-FX

transceivers on Ports 3, 4, one SW5-MII and one

P5-MII interface

All registers of MACs and PHYs units can be

managed by the SPI or the SMI interface. MIIM

registers can be accessed through the MDC/MDIO

interface. EEPROM can set all control registers for the

unmanaged mode. KSZ8895MQ/RQ/FMQ are 128-pin

PQFP packages.

Functional Diagram

Note:

SW5 indicates the MAC5 of the switch side, P5 indicates the PHY5 of the Port 5.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

March 19, 2014

Revision 1.7

Summary of content (119 pages)

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KSZ8895MQ/RQ/FMQ Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface Revision 1.7 General Description The KSZ8895MQ/RQ/FMQ is a highly-integrated, Layer 2 managed, five-port switch with numerous features designed to reduce system cost.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Features Advanced Switch Features • On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table). • IEEE 802.1q VLAN support for up to 128 active VLAN groups (full-range 4096 of VLAN IDs). • • Full duplex IEEE 802.3x flow control (PAUSE) with force mode option. Static MAC table supports up to 32 entries. • • Half-duplex back pressure flow control.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Contents System Level Applications ...........................................................................................................................................13 Pin Configuration ..........................................................................................................................................................15 Pin Description ................................................................................................................
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Port 5 PHY 5 P5-MII/RMII Interface............................................................................................................................38 Port 5 MAC 5 SW5-MII Interface for the KSZ8895MQ/FMQ ......................................................................................39 Port 5 MAC 5 Switch SW5-RMII Interface for the KSZ8895RQ .................................................................................40 SNI Interface Operation ............
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers .............................................................................................................................................................65 Register 16 (0x10): Port 1 Control 0 .......................................................................................................................65 Register 32 (0x20): Port 2 Control 0 .............................................................................................................
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Register 60 (0x3C): Port 3 Control 5 ......................................................................................................................70 Register 76 (0x4C): Port 4 Control 5 ......................................................................................................................70 Register 92 (0x5C): Port 5 Control 5 ......................................................................................................................
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Register 134 (0x86): Global Control 18 ..................................................................................................................78 Register 135 (0x87): Global Control 19 ..................................................................................................................79 Register 144 (0x90): TOS Priority Control Register 0 ............................................................................................
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Register 181 (0xB5): Port 1 Control 13 ..................................................................................................................86 Register 197 (0xC5): Port 2 Control 13 ..................................................................................................................86 Register 213 (0xD5): Port 3 Control 13 ..................................................................................................................
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Register 253 (0xFD): Port 5 Queue 2 Egress Limit Control 3 ................................................................................88 Register 190 (0xBE) : Port 1 Queue 3 Egress Limit Control 4 ...............................................................................89 Register 206 (0xCE) : Port 2 Queue 3 Egress Limit Control 4 ...............................................................................
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Micrel, Inc. KSZ8895MQ/RQ/FMQ List of Figures Figure 1. Broadband Gateway ..................................................................................................................................... 13 Figure 2. Integrated Broadband Router ....................................................................................................................... 13 Figure 3. Standalone Switch ..............................................................................................................
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Micrel, Inc. KSZ8895MQ/RQ/FMQ List of Tables Table 1. MDI/MDI-X Pin Definitions ............................................................................................................................. 28 Table 2. Internal Function Block Status ....................................................................................................................... 31 Table 3. Port 5 PHY P5-MII/RMII Signals ..................................................................................................
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Switch Controller On-Chip Frame Buffers System Level Applications SPI/GPIO 10/100 MAC 1 10/100 PHY 1 10/100 MAC 2 10/100 PHY 2 10/100 MAC 3 10/100 PHY 3 10/100 MAC 4 10/100 PHY 4 10/100 MAC 5 10/100 PHY 5 4-port LAN 1-port WAN I/F SPI Ethernet MAC MII-SW MII-P5 CPU Ethernet MAC External WAN port PHY not required. Switch Controller On-Chip Frame Buffers Figure 1. Broadband Gateway WAN PHY & AFE (xDSL, CM...
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KSZ8895MQ/RQ/FMQ Switch Controller On-Chip Frame Buffers Micrel, Inc. 10/100 MAC 1 10/100 PHY 1 10/100 MAC 2 10/100 PHY 2 10/100 MAC 3 10/100 PHY 3 10/100 MAC 4 10/100 PHY 4 10/100 MAC 5 10/100 PHY 5 5-port LAN Figure 3. Standalone Switch Figure 4. Using KSZ8895FMQ for Dual Media Converter March 12, 2014 14 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin Description (1) Port Pin Name Type 1 MDI-XDIS IPD 2 GNDA GND 3 VDDAR P 4 RXP1 I 1 Physical receive signal + (differential). 5 RXM1 I 1 Physical receive signal - (differential). 6 GNDA GND 7 TXP1 O 1 Physical transmit signal + (differential). 8 TXM1 O 1 Physical transmit signal - (differential). 1−5 Pin Function (2) Pin Number Disable auto MDI/MDI-X. PD (default) = normal operation. PU = disable auto MDI/MDI-X on all ports.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin Description (Continued) Type (1) Port (2) Pin Number Pin Name 39 FXSD4 IPD 40 NC NC Pin Function FMQ: Fiber signal detect pin for Port 4. MQ/RQ: no connection. No connect. 41 NC NC No connect. 42 NC NC No connect. 43 NC NC No connect. 44 NC NC No connect. 45 NC NC No connect. 46 NC NC No connect. 47 PWRDN_N IPU Full-chip power down. Active low. 48 INTR_N OPU Interrupt. This pin is Open-Drain output pin.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin Description (Continued) Pin Number Pin Name Type (1) Port Pin Function (2) PHY[5] MII/RMII receive bit 1. 64 PMRXD1 IPD/O 5 Strap option: PD (default) = drop excessive collision packets. PU = does not drop excessive collision packets. PHY[5] MII/RMII receive bit 0. Strap option: 65 PMRXD0 IPD/O 5 PD (default) = disable aggressive back-off algorithm in half-duplex mode. PU = enable for performance enhancement.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin Description (Continued) Pin Name 78 SMRXC I/O 79 SMRXDV/SMCRSDV IPD/O 80 SMRXD3 IPD/O 81 SMRXD2 IPD/O 82 SMRXD1 IPD/O 83 SMRXD0 IPD/O 84 SCOL IPD/O 85 SCRS IPD/O March 12, 2014 Type (1) Pin Number Port (2) Pin Function MQ/FMQ: Port 5 Switch MII receive clock, Input: SW5-MII MAC mode, Output: SW5-MII PHY mode.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin Description (Continued) Pin Number Pin Name Type (1) Port (2) Pin Function Pins 91, 86, and 87 are dual MII/RMII configuration pins for the Port 5 MAC5 MII/RMII and PHY[5] MII/RMII. SW5-MII supports both MAC mode and PHY modes. P5-MII supports PHY mode only. See pins configuration below.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin Description (Continued) Type (1) Pin Number Pin Name Port 100 VDDIO P 101 LED2-2 IPU/O 2 102 LED2-1 IPU/O 2 103 LED2-0 IPU/O 2 104 LED1-2 IPU/O 1 105 LED1-1 IPU/O 1 106 LED1-0 IPU/O 1 107 MDC IPU All 108 MDIO IPU/O All Pin Function (2) 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry. LED indicator 2.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin Description (Continued) Pin Number Pin Name Type (1) Port Pin Function (2) Serial bus configuration pin. For this case, if the EEPROM is not present, the KSZ8895MQ/RQ/FMQ will start itself with the PS[1.0] = 00 default register values. 113 Notes: 1. PS1 IPD Pin Configuration Serial Bus Configuration PS[1.0] = 00 I C Master Mode for EEPROM PS[1.0] = 01 SMI Interface Mode PS[1.0] = 10 SPI Slave Mode for CPU Interface PS[1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin for Strap-In Options The KSZ8895MQ/RQ/FMQ can function as a managed switch or an unmanaged switch. If no EEPROM or microcontroller exists, then the KSZ8895MQ/RQ/FMQ will operate from its default setting. The strap-in option pins can be configured by external pull-up/down resistors and take effect after power down reset or warm reset. The functions are described in the following table.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin for Strap-In Options (Continued) Pin # Pin Name (1) PU/PD (1) Description Switch MII receive bit 0. Strap option: LED mode PD (default) = mode 0; PU = mode 1. See “Register 11.” 83 SMRXD0 Mode 0 Mode 1 LEDX_2 Lnk/Act 100Lnk/Act LEDX_1 Fulld/Col 10Lnk/Act LEDX_0 Speed Fulld IPD/O Pin 91,86,87 are dual MII/RMII configuration pins for the Port 5 MAC 5 MII/RMII and PHY[5] MII/RMII. SW5-MII supports both MAC mode and PHY modes. P5MII supports PHY mode only.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin for Strap-In Options (Continued) Pin # Pin Name (1) PU/PD 101 LED2-2 IPU/O 102 LED2-1 IPU/O 105 LED1-1 IPU/O 106 LED1-0 IPU/O 113 PS1 IPD (1) Description LED2 indicator 2. Strap option for KSZ8895RQ only: PU (default) = Select the device as clock mode in RQ SW5- RMII, 25MHz crystal to X1/X2 pins of the device and REFCLK output 50MHz clock. PD = Select the device as normal mode in SW5-RMII. Switch MAC5 used only.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Introduction The KSZ8895MQ/RQ/FMQ contains five 10/100 physical layer transceivers and five media access control (MAC) units with an integrated Layer 2 managed switch. The device runs in three modes. The first mode is as a five-port integrated switch. The second is as a five-port switch with the fifth port decoupled from the physical port. In this mode, access to the fifth MAC is provided through a media independent interface (MII/RMII).
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Micrel, Inc. KSZ8895MQ/RQ/FMQ PLL Clock Synthesizer The KSZ8895MQ/RQ/FMQ generates 125MHz, 83MHz, 41MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal or oscillator. Scrambler/Descrambler (100BASE-TX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR).
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Micrel, Inc. KSZ8895MQ/RQ/FMQ MDI MDI-X RJ-45 Pins Signals RJ-45 Pins Signals 1 TD+ 1 RD+ 2 TD- 2 RD- 3 RD+ 3 TD+ 6 RD- 6 TD- Table 1. MDI/MDI-X Pin Definitions Straight Cable A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 6 depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X). Figure 6. Typical Straight Cable Connection March 12, 2014 28 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Crossover Cable A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. Figure 7 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices). Figure 7. Typical Crossover Cable Connection Auto-Negotiation The KSZ8895MQ/RQ/FMQ conforms to the auto-negotiation protocol as described by the 802.3 committee.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Figure 8. Auto-Negotiation March 12, 2014 30 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ On-Chip Termination Resistors The KSZ8895MQ/RQ/FMQ reduces the board cost and simplifies the board layout by using on-chip termination resistors for all ports and RX/TX differential pairs without the external termination resistors. The combination of the on-chip termination and internal biasing will save about 500 to 1000mw in power consumption as compared to using external biasing and termination resistors, and the transformer will not consume power any more.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Energy Detect Mode Energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8895MQ/RQ/FMQ port is not connected to an active link partner. In this mode, the device will save more power when the cables are unplugged. If the cable is not plugged in, the device can automatically enter a low power state— the energy detect mode. In this mode, the device will keep transmitting 120ns width pulses at 1 pulse/s rate.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information. The KSZ8895MQ/RQ/FMQ is guaranteed to learn 1K addresses and distinguishes itself from a hash-based look-up table, which, depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Inter-Packet Gap (IPG) If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN. Backoff Algorithm The KSZ8895MQ/RQ/FMQ implements the IEEE Standard 802.3 binary exponential backoff algorithm, and optional “aggressive mode” backoff.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Figure 9. Destination Address Lookup Flow Chart, Stage 1 March 12, 2014 35 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Figure 10. Destination Address Resolution Flow Chart, Stage 2 March 12, 2014 36 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ The KSZ8895MQ/RQ/FMQ will not forward the following packets: 1. Error packets These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet errors. 2. IEEE802.3x PAUSE frames KSZ8895MQ/RQ/FMQ intercepts these packets and performs full duplex flow control accordingly. 3.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ MII Interface Operation The media-independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface between physical layer and MAC layer devices. The KSZ8895MQ/RQ/FMQ provides two such interfaces. The P5-MII interface is used to connect to the fifth PHY, where as the SW-MII interface is used to connect to the fifth MAC. Each of these MII interfaces contains two distinct groups of signals, one for transmission and the other for receiving.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Port 5 MAC 5 SW5-MII Interface for the KSZ8895MQ/FMQ Table 4 shows two connection manners: 1. The first is an external MAC connects to SW5-MII PHY mode. 2. The second is an external PHY connects to SW5-MII MAC mode. Please see the pin [91, 86, 87] descriptions for configuration details for the MAC mode and PHY mode. SW5-MII works with 25MHz clock for 100Base-TX, SW5-MII works with 2.5MHz clock for 10Base-T.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Port 5 MAC 5 Switch SW5-RMII Interface for the KSZ8895RQ The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). The KSZ8895RQ supports RMII interface at Port 5 switch side and provides a common interface at MAC5 layer in the device, and has the following key characteristics: • Supports 10Mbps and 100Mbps data rates.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Functionality QoS Priority Support The KSZ8895MQ/RQ/FMQ provides Quality of Service (QoS) for applications such as VoIP and video conferencing. The KSZ8895MQ/RQ/FMQ offers one, two, or four priority queues per port by setting the port registers xxx control 9 bit 1 and the port registers xxx control 0 bit 0, the 1/2/4 queues split as follows, [Port registers xxx control 9 bit 1, control 0 bit 0] = 00 single output queue as default.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ The KSZ8895MQ/RQ/FMQ provides the option to insert or remove the priority tagged frame's header at each individual egress port. This header, consisting of the two-byte VLAN Protocol ID (VPID) and the two-byte Tag Control Information field (TCI), is also referred to as the IEEE 802.1Q VLAN tag.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details. Address learning is enabled on the port in this state. Forwarding state: packets are forwarded and received normally.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Tail Tagging Mode The Tail Tag is only seen and used by the Port 5 interface, which should be connected to a processor by SW5MII/RMII interface. The one byte tail tagging is used to indicate the source/destination port in Port 5. Only bit [3−0] are used for the destination in the tail tagging byte. Other bits are not used. The Tail Tag feature is enabled by setting register 12 bit 1. Figure 12.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ IGMP Support There are two parts involved to support the Internet Group Management Protocol (IGMP) in Layer 2. The first part is IGMP snooping, the second part is this IGMP packet to be sent back to the subscribed port. Describe them as follows. • IGMP Snooping The KSZ8895MQ/RQ/FMQ traps IGMP packets and forwards them only to the processor (Port 5 SW5-MII/RMII). The IGMP packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ DA found in Static MAC table USE FID Flag? FID Match? DA+FID found in Dynamic MAC table No Do Not care Do Not care No No Do Not care Do Not care Yes Yes 0 Do Not care Do Not care Yes 1 No No Yes 1 No Yes Yes 1 Yes Do Not care Action Broadcast to the membership ports defined in the VLAN table bit[11:7]. Send to the destination port defined in the dynamic MAC table bit[58:56].
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Egress Rate Limit For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic. Interframe gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each output priority queue is limited by the egress rate specified by the data rate selection table followed the egress rate limit control registers.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Figure 13. KSZ8895MQ/RQ/FMQ EEPROM Configuration Timing Diagram To configure the KSZ8895MQ/RQ/FMQ with a pre-configured EEPROM use the following steps: 1. At the board level, connect pin 110 on the KSZ8895MQ/RQ/FMQ to the SCL pin on the EEPROM. Connect pin 111 on the KSZ8895MQ/RQ/FMQ to the SDA pin on the EEPROM. 2. A[2-0] address pins of EEPROM should be tied to ground for address A[2-0] = ‘000’ to be identified by the KSZ8895MQ/RQ/FMQ. 3.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ To use the KSZ8895MQ/RQ/FMQ SPI: 1. At the board level, connect KSZ8895MQ/RQ/FMQ pins as follows: KSZ8895MQ/RQ/FMQ Pin Number KSZ8895MQ/RQ/FMQ Signal Name 112 SPIS_N 110 SPIC SPI Clock 111 SPID Master Out Slave Input 109 SPIQ Master In Slave Output Microprocessor Signal Description SPI Slave Select Table 10. SPI Connections 2. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “10” to set the serial configuration to SPI slave mode. 3.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ SPIS_N SPIC SPID X A1 A2 A3 A4 A5 A6 A7 0 1 0 0 0 0 0 0 A0 D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 SPIQ WRITE COMMAND WRITE ADDRESS Byte 1 SPIS_N SPIC SPID D7 D6 D5 D4 D4 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D7 D0 D6 D5 D4 D3 SPIQ Byte 2 Byte N Byte 3 ... Figure 16.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ MII Management Interface (MIIM) The KSZ8895MQ/RQ/FMQ supports the standard IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8895MQ/RQ/FMQ. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY settings. Further details on the MIIM interface are found in Clause 22.2.4.5 of the IEEE 802.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ SMI register Read access is selected when OP Code is set to “10” and bits [2:1] of the PHY address is set to ‘11’. The 8-bit register address is the concatenation of {PHY address bits [4:3], PHY address bits [0], REG address bit [4:0]}. TA is turn-around bits.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Register Description Offset Decimal Hex Description 0−1 0x00-0x01 Chip ID Registers. 2−13 0x02-0x0D Global Control Registers. 14−15 0x0E-0x0F Power Down Management Control Registers. 16−20 0x10-0x14 Port 1 Control Registers. 21−24 0x15-0x18 Port 1 Reserved (Factory Test Registers). 25−31 0x19-0x1F Port 1 Control/Status Registers. 32−36 0x20-0x24 Port 2 Control Registers. 37−40 0x25-0x28 Port 2 Reserved (Factory Test Registers).
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Register Description (Continued) Offset Decimal 192−206 Hex 0xC0-0xCE 207 208−222 0xCF 0xD0-0xDE 223 224−238 0xDF 0xE0-0xEE 239 240−254 Description 0xEF 0xF0-0xFE 255 March 12, 2014 0xFF Port 2 Control Registers. Reserved (Factory Testing Register). Port 3 Control Registers. Reserved (Factory Testing Register). Port 4 Control Registers. Reserved (Factory Testing Register). Port 5 Control Registers. Reserved (Factory Testing Register). 55 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers Address Name Description Mode Default Chip family. RO 0x95 0100 = KSZ8895MQ/FMQ 0110 = KSZ8995RQ RO 0x4 is for MQ/FMQ 0x6 is RQ Revision ID RO 0x0 Register 0 (0x00): Chip ID0 7−0 Family ID Register 1 (0x01): Chip ID1 / Start Switch 7−4 Chip ID 3−1 Revision ID 0 Start Switch 1, start the chip when external pins (PS1, PS0) = (1,0) Note: in (PS1,PS0) = (0,0) mode, the chip will start automatically, after trying to read the external EEPROM.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers (Continued) Address Name 3 Enable PHY MII/RMII 2 Reserved 1 UNH Mode 0 Link Change Age Description Mode Default 1, enable PHY P5-MII/RMII interface (default). Note: if not enabled, the switch will tri-state all outputs. R/W 1 Pin LED[5][1] strap option. PD(0): isolate. PU(1): Enable. Note: LED[5][1] has internal pullup (PU). N/A Do not change.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers (Continued) Address Name Description 3 Frame Length Field Check 1, will check frame length field in the IEEE packets If the actual length does not match, the packet will be dropped (for L/T <1500) . Mode Default R/W 0 2 Aging Enable 1, Enable age function in the chip. 0, Disable aging function. R/W 1 Fast age Enable 1 = Turn on fast age (800µs). R/W 1 Pin LED[5][2] strap option. PD(0): Aging disable. PU(1): Aging enable (default).
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers (Continued) Address 4 3 2 Name Description Flow Control and Back Pressure fair Mode 1, fair mode is selected. In this mode, if a flow control port and a non-flow control port talk to the same destination port, then packets from the non-flow control port may be dropped. This is to prevent the flow control port from being flow controlled for an extended period of time.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers (Continued) Address Name Description 4 Enable Pre-Tag on Switch SW5-MII/RMII Interface 3−2 1 Mode Default 1, packets forwarded to Switch MII/RMII interface will be pre-tagged with the source port number (preamble before MRXDV). 0, normal operation. R/W 0 Reserved N/A RO 00 Enable “Tag” Mask 1, the last 5 digits in the VID field are used as a mask to determine which port(s) the packet should be forwarded to. 0, no tag masks.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers (Continued) Address Name Description Mode Default 4 Switch SW5-MII/RMII Speed 1, the switch SW5-MII/RMII is in 10Mbps mode. 0, the switch SW5-MII/RMII is in 100Mbps mode. R/W 0 Pin SMRXD1 strap option. PD(0): (default) Enable 100Mbps. PU(1): Enable 10Mbps. Note: SMRXD1 has internal pulldown. 3 Null VID Replacement 1, will replace null VID with port VID (12 bits). 0, no replacement for null VID.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers (Continued) Address Name Description Mode Default RO 0x00 RO 0 R/W 0 Register 10 (0x0A): Global Control 8 7−0 Factory Testing N/A Do not change. Register 11 (0x0B): Global Control 9 7 6 Reversed Port 5 SW5- RMII reference clock edge select N/A Do not change.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers (Continued) Address Name Description Mode Default RO 0 RO 1 Pin LED[2][2] strap option. PD(0): Select SW5-RMII at normal mode to receive external 50MHz RMII reference clock PU(1): (default) Select SW5RMII at clock mode, RMII output 50MHz Note: LED[2][2] has internal pullup.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers (Continued) Address Name Description 5 PLL Power Down Pll power down enable: 1 = Enable 0 = Disable 4–3 Power Management Mode Power management mode : 00 = Normal mode (D0) 01 = Energy Detection mode (D2) 10 = soft Power Down mode (D3) 11 = Power Saving mode (D1) 2−0 Reserved N/A Do not change. Mode Default R/W 0 R/W 00 Pin LED[4][0] strap option.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers (Continued) Address 0 Name Description Two Queues Split Enable This bit 0 in the register16/32/48/64/80 should be in combination with Register177/193/209/225/241 bit 1 for Port 1-5 will select the split of ½/4 queues: For Port 1, [Register 177 bit 1, Register 16 bit 0] = [11], Reserved [10], the port output queue is split into four priority queues or if map 802.1p to priority 0-3 mode.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers (Continued) Register 27 (0x1B): Reserved Register 43 (0x2B): Reserved Register 59 (0x3B): Reserved Register 75 (0x4B): Reserved Register 91 (0x5B): Reserved Address Name Description 7−0 Reserved N/A Do not change.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers (Continued) Address Name Description Mode Default 4 Advertised Flow Control Capability 1, advertise flow control capability. 0, suppress flow control capability from transmission to link partner. R/W 1 3 Advertised 100BT FullDuplex Capability 1, advertise 100BT full-duplex capability. 0, suppress 100BT full-duplex capability from transmission to link partner.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers (Continued) Register 30 (0x1E): Port 1 Status 1 Register 46 (0x2E): Port 2 Status 1 Register 62 (0x3E): Port 3 Status 1 Register 78 (0x4E): Port 4 Status 1 Register 94 (0x5E): Port 5 Status 1 Address Name 7 MDIX Status 6 AN Done 5 Link Good 4 3 2 1 0 Partner Flow Control Capability Partner 100BT FullDuplex Capability Partner 100BT HalfDuplex Capability Partner 10BT Full-Duplex Capability Partner 10BT Half-Duplex Capability Description 1, MDI.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, or the MIB counters. Address Name Description Mode Default Register 110 (0x6E): Indirect Access Control 0 7−5 Reserved Reserved. R/W 000 4 Read High Write Low 1, read cycle. 0, write cycle. R/W 0 3−2 Table Select 00 = static mac address table selected. 01 = VLAN table selected.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default R/W 00000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 Register 112 (0x70): Indirect Data Register 8 68−64 Indirect Data Bit 68-64 of indirect data. Register 113 (0x71): Indirect Data Register 7 63−56 Indirect Data Bit 63-56 of indirect data.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default RO 0 RO 000 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 1, Port 1 interrupt request 0, normal 0 Port 1 Interrupt Status Note: This bit is set by Port 1 link change. Write a “1” to clear this bit Register 125 (0x7D): Interrupt Mask Register 7–5 Reserved 4 Port 5 Interrupt Mask 3 Port 4 Interrupt Mask 2 Port 3 Interrupt Mask 1 Port 2 Interrupt Mask 0 Port 1 Interrupt Mask Reserved.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default Register 130 (0x82): Global Control 14 When the 2 Queues configuration is selected, these Pri_2Q[1:0] bits are used to map the 2-bit result of IEEE 802.1p from register 128/129 or TOS/DiffServ from register 144- 159 mapping (for 4 Queues) into two queues low/high priorities. Pri_2Q[1:0] 7–6 (Note that program Prio_2Q[1:0] = 01 is not supported and should be avoided) 2-bit result of IEEE 802.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default Register 132 (0x84): Global Control 16 7–6 Chip I/O output drive strength select[1:0] 5 Unknown multicast packet forward (not including IP multicast packet) 4–0 Unknown multicast packet forward port map R/W 01 Pin LED[3][0] strap option. Pull-down (0): Select 12mA drive strength. Pull-up (1): Select 8mA drive strength. Note: LED[3][0] has internal pull-up.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address 4–0 Name Description Mode Unknown IP multicast packet forward port map 00000 = filter unknown IP multiicast packet 00001 = forward unknown IP multicast packet to port 1. 00010 = forward unknown IP multicast packet to port 2.
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Micrel, Inc. Address KSZ8895MQ/RQ/FMQ Name Description Mode Default RO 0x80 RO 0x15 R/W 0x0C N/A Do not change. RO 0x32 Reserved N/A Do not change. RO 0 Invert phase of SMTXC clock input for SW5-RMII (Used for KSZ8895RQ only) 1 = Invert the phase of SMTXC clock input in RMII mode, set this bit at normal mode device when connect two devices with SW5-RMII back to back connection case only. Please see strap pin LED2_2 for normal mode.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Static MAC Address Table KSZ8895MQ/RQ/FMQ has a static and a dynamic address table. When a DA look-up is requested, both tables will be searched to make a packet forwarding decision. When an SA look-up is requested, only the dynamic table is searched for aging, migration, and learning purposes. The static DA look-up result will have precedence over the dynamic DA look-up result. If there are DA matches in both tables, the result from the static table will be used.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ VLAN Table The VLAN table is used for VLAN table look-up. If 802.1q VLAN mode is enabled (Register 5 bit 7 = 1), this table is used to retrieve VLAN information that is associated with the ingress packet. There are three fields for FID (filter ID), Valid, and VLAN membership in the VLAN table. The three fields must be initialized before the table is used. There is no VID field because 4096 VIDs are used as a dedicated memory address index into a 1024x52-bit memory space.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Dynamic MAC Address Table This table is read only. The contents are maintained by the KSZ8895MQ/RQ/FMQ only. Address Name Description Mode Default RO 1 RO 0 Format of Dynamic MAC Address Table (1K entries) 71 MAC Empty 70−61 No of Valid Entries 60-59 Time Stamp 1, there is no valid entry in the table. 0, there are valid entries in the table. Indicates how many valid entries in the table.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ MIB (Management Information Base) Counters The MIB counters are provided on per port basis. These counters are read using indirect memory access as below: For Port 1 Offset Counter Name Description 0x0 RxLoPriorityByte Rx lo-priority (default) octet count including bad packets. 0x1 RxHiPriorityByte Rx hi-priority octet count including bad packets. 0x2 RxUndersizePkt Rx undersize packets w/good CRC.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ For port 2, the base is 0x20, same offset definition (0x20-0x3f) For port 3, the base is 0x40, same offset definition (0x40-0x5f) For port 4, the base is 0x60, same offset definition (0x60-0x7f) For port 5, the base is 0x80, same offset definition (0x80-0x9f) Address Name Description Mode Default RO 0 RO 0 RO 0 Mode Default Format of Per Port MIB Counters (16 entries) 31 Overflow 30 Count Valid 29−0 Counter Values 1, Counter overflow.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ The KSZ8895MQ/RQ/FMQ provides a total of 34 MIB counters per port. These counters are used to monitor the port detail activity for network management and maintenance. These MIB counters are read using indirect memory access, per the following examples.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ MIIM Registers All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping mechanisms are used for MIIM and SPI. The “PHYAD” defined in IEEE is assigned as “0x1” for Port 1, “0x2” for Port 2, “0x3” for Port 3, “0x4” for Port 4, and “0x5” for Port 5. The “REGAD” supported are 0x0-0x5 (0h-5h), 0x1D (1dh) and 0x1F (1fh). Address Name Description Mode Default 1, PHY soft reset. 0, Normal operation.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ MIIM Registers (Continued) Address Name Description Mode Default RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 Register 1h: MII Status 15 T4 Capable 14 100 Full Capable 13 100 Half Capable 12 10 Full Capable 11 10 Half Capable 10−7 Reserved 6 Preamble Suppressed 0, Not 100 BASET4 capable. 1, 100BASE-TX full-duplex capable. 0, Not capable of 100BASE-TX full-duplex. 1, 100BASE-TX half-duplex capable.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ MIIM Registers (Continued) Address Name Description Mode Default Register 5h: Link Partner Ability 15 Next Page Not supported. RO 0 14 LP ACK Not supported. RO 0 13 Remote fault Not supported. RO 0 12−11 Reserved RO 0 10 Pause RO 0 9 Reserved RO 0 Address Name Mode Default RO 0 RO 0 RO 0 RO 0 RO 00001 8 Adv 100 Full 7 Adv 100 Half 6 Adv 10 Full 5 Adv 10 Half 4-0 Reserved 1, link partner flow control capable.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ MIIM Registers (Continued) Address Name Description Mode Default 1 Remote Loopback 1, Perform Remote loopback, loop back path as follows: Port 1 (PHY ID address 0x1 reg. 1f, bit 1 = ‘1’) Start: RXP1/RXM1 (port 1) Loopback: PMD/PMA of port 1’s PHY End: TXP1/TXM1 (port 1) Setting PHY ID address 0x2,3,4,5 reg. 1f, bit 1 = ‘1’ will perform remote loopback on port 2, 3, 4, 5. 0, Normal Operation. R/W 0 0 Reserved N/A RO 0 March 12, 2014 103 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VDDAR, VDDAP, VDDC) ....................... –0.5V to +2.4V (VDDAT, VDDIO) ................................. –0.5V to +4.0V Input Voltage ........................................ –0.5V to +4.0V Output Voltage ..................................... –0.5V to +4.0V Lead Temperature (soldering, 10 sec.) .............. 260°C Storage Temperature (TS) .................–55°C to +150°C HBM ESD Rating.....................
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Electrical Characteristics(4, 5) (Continued) VIN = 1.2V/3.3V (typ.); TA = 25°C Symbol Parameter Condition Min. Typ. Max. Units CMOS Inputs VIH Input High Voltage (VDDIO=3.3/2.5/1.8V) VIL Input Low Voltage (VDDIO=3.3/2.5/1.8V) IIN Input Current (Excluding Pull-up/Pull-down) 2.0/1.8 /1.3 VIN = GND ~ VDDIO V 0.8/0.7 /0.5 10 –10 V µA CMOS Outputs VOH Output High Voltage (VDDIO=3.3/2.5/1.8V) IOH = –8mA VOL Output Low Voltage (VDDIO=3.3/2.5/1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Timing Diagrams EEPROM Timing Figure 18. EEPROM Interface Input Receive Timing Diagram Figure 19. EEPROM Interface Output Transmit Timing Diagram Symbol Parameter Min. Typ. Max. tCYC1 Clock Cycle tS1 Set-Up Time 20 ns tH1 Hold Time 20 ns tOV1 Output Valid 16384 4096 4112 Units ns 4128 ns Table 23. EEPROM Timing Parameters March 12, 2014 106 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ SNI Timing Figure 20. SNI Input Timing Figure 21. SNI Output Timing Symbol Parameter Min. Typ. Max. tCYC2 Clock Cycle tS2 Set-Up Time 10 ns tH2 Hold Time 0 ns tO2 Output Valid 0 100 3 Units ns 6 ns Table 24. SNI Timing Parameters March 12, 2014 107 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ MII Timing Figure 22. MAC Mode MII Timing – Data Received from MII Figure 23. MAC Mode MII Timing – Data Transmitted from MII 10Base-T/100Base-TX Symbol Parameter Min. Typ. Max. tCYC3 Clock Cycle tS3 Set-Up Time 10 ns tH3 Hold Time 5 ns tOV3 Output Valid 3 400/40 9 Units ns 25 ns Table 25. MAC Mode MII Timing Parameters March 12, 2014 108 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ MII Timing (Continued) Figure 24. PHY Mode MII Timing – Data Received from MII Figure 25. PHY Mode MII Timing – Data Transmitted from MII 10BaseT/100BaseT Symbol Parameter tCYC4 Clock Cycle tS4 Set-Up Time Min. Typ. Max. 400/40 ns 10 tH4 Hold Time 0 tOV4 Output Valid 16 Units ns ns 20 25 ns Table 26. PHY Mode MII Timing Parameters March 12, 2014 109 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ RMII Timing Figure 26. RMII Timing – Data Received from RMII Figure 27. RMII Timing – Data Transmitted to RMII Timing Parameter Description Min. Typ. Max. tcyc Clock cycle t1 Setup time 4 ns t2 Hold time 2 ns tod Output delay 3 20 Unit ns 14 ns Table 27. RMII Timing Parameters March 12, 2014 110 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ SPI Timing Figure 28. SPI Input Timing Symbol Parameter Min. Typ. Max.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ SPI Timing (Continued) Figure 29. SPI Output Timing Symbol Parameter Min. fC Clock Frequency tCLQX SPIQ Hold Time tCLQV Clock Low to SPIQ Valid tCH Clock High Time 18 ns tCL Clock Low Time 18 ns tQLQH SPIQ Rise Time 50 ns tQHQL SPIQ fall Time 50 ns tSHQZ SPIQ Disable Time 15 ns 0 Typ. Max. Units 25 MHz 0 ns 15 ns Table 29. SPI Output Timing Parameters March 12, 2014 112 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Auto-Negotiation Timing Figure 30. Auto-Negotiation Timing Symbols Parameters Min. Typ. Max. Units tBTB FLP burst to FLP burst 8 16 24 ms tFLPW FLP burst width tPW Clock/Data pulse width tCTD Clock pulse to Data pulse 55.5 64 69.5 µs tCTC Clock pulse to Clock pulse 111 128 139 µs Number of Clock/Data pulse per burst 17 2 ms 100 ns 33 Table 30. Auto-Negotiation Timing Parameters March 12, 2014 113 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ MDC/MDIO Timing Figure 31. MDC/MDIO Timing Timing Parameter Description Min. Typ. tP MDC period t1MD1 MDIO (PHY input) setup to rising edge of MDC 10 ns tMD2 MDIO (PHY input) hold from rising edge of MDC 4 ns tMD3 MDIO (PHY output) delay from rising edge of MDC 400 222 Max Unit ns ns Table 31. MDC/MDIO Typical Timing Parameters March 12, 2014 114 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Reset Timing Figure 32. Reset Timing Symbol Parameter Min. Typ. Max. Units tSR Stable Supply Voltages to Reset High 10 ms tCS Configuration Set-Up Time 50 ns tCH Configuration Hold Time 50 ns tRC Reset to Strap-In Pin Output 50 ns tvr 3.3V rise time 100 us Table 32. Reset Timing Parameters March 12, 2014 115 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Reset Circuit Diagram Micrel recommends the following discrete reset circuit as shown in Figure 22 when powering up the KS8895MQ device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit as shown in Figure 23. Figure 33. Recommended Reset Circuit Figure 34.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Selection of Isolation Transformer(1) One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated commonmode choke is recommended for exceeding FCC requirements at line side. Request to separate the center taps of RX/TX at chip side. The following table gives recommended transformer characteristics. Characteristics Name Value Turns Ratio Test Condition 1 CT : 1 CT Open-Circuit Inductance (min.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ Package Information(1) 128-Pin PQFP Package Note: 1. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com. March 12, 2014 118 Revision 1.
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Micrel, Inc. KSZ8895MQ/RQ/FMQ MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice.