Specifications

Micrel, Inc.
KSZ8895MQ/RQ/FMQ
MII Management Interface (MIIM)
The KSZ8895MQ/RQ/FMQ supports the standard IEEE 802.3 MII Management Interface, also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control
the states of the KSZ8895MQ/RQ/FMQ. An external device with MDC/MDIO capability is used to read the PHY
status or configure the PHY settings. Further details on the MIIM interface are found in Clause 22.2.4.5 of the IEEE
802.3u Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the data line (pin 108 MDIO) and the clock line (pin 107 MDC).
• A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KSZ8895MQ/RQ/FMQ device.
• Access to a set of eight 16-bit registers, consisting of 8 standard MIIM registers [0:5h], 1d and 1f MIIM
registers per port.
The MIIM Interface can operate up to a maximum clock speed of 10MHz MDC clock.
Table 11 depicts the MII Management Interface frame format.
Preamble
Start of
Frame
Read/Write
OP Code
PHY
Address
Bits[4:0]
REG
Address
Bits[4:0]
TA Data Bits[15:0] Idle
Read
32 1’s 01 10 AAAAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z
Write
32 1’s 01 01 AAAAA RRRRR 10 DDDDDDDD_DDDDDDDD Z
Table 11. MII Management Interface Frame Format
The MIIM interface does not have access to all the configuration registers in the KSZ8895MQ/RQ/FMQ. It can only
access the standard MIIM registers. See “MIIM Registers”. The SPI interface and MDC/MDIO SMI mode, on the
other hand, can be used to access all registers with the entire KSZ8895MQ/RQ/FMQ feature set.
Serial Management Interface (SMI)
The SMI is the KSZ8895MQ/RQ/FMQ non-standard MIIM interface that provides access to all KSZ8895MQ/RQ/FMQ
configuration registers. This interface allows an external device with MDC/MDIO interface to completely monitor and
control the states of the KSZ8895MQ/RQ/FMQ.
The SMI interface consists of the following:
• A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
• A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with the KSZ8895MQ/RQ/FMQ device.
• Access to all KSZ8895MQ/RQ/FMQ configuration registers. Register access includes the Global, Port and
Advanced Control Registers 0-255 (0x00 – 0xFF), and indirect access to the standard MIIM registers [0:5] and
custom MIIM registers [29, 31].
The SMI Interface can operate up to a maximum clock speed of 10MHz MDC clock.
Table 12 depicts the SMI frame format.
Preamble
Start of
Frame
Read/Write
OP Code
PHY
Address
Bits[4:0]
REG
Address
Bits[4:0]
TA Data Bits[15:0] Idle
Read
32 1’s 01 10 RR11R RRRRR Z0 0000_0000_DDDD_DDDD Z
Write
32 1’s 01 01 RR11R RRRRR 10 xxxx_xxxx_DDDD_DDDD Z
Table 12. Serial Management Interface (SMI) Frame Format
March 12, 2014
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Revision 1.7