Specifications

Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Advanced Control Registers (Continued)
Address Name Description Mode Default
Register 112 (0x70): Indirect Data Register 8
68−64
Indirect Data Bit 68-64 of indirect data. R/W 00000
Register 113 (0x71): Indirect Data Register 7
63−56
Indirect Data Bit 63-56 of indirect data. R/W 00000000
Register 114 (0x72): Indirect Data Register 6
55−48
Indirect Data Bit 55-48 of indirect data. R/W 00000000
Register 115 (0x73): Indirect Data Register 5
47−40
Indirect Data Bit 47-40 of indirect data. R/W 00000000
Register 116 (0x74): Indirect Data Register 4
39−32
Indirect Data Bit 39-32 of indirect data. R/W 00000000
Register 117 (0x75): Indirect Data Register 3
31−24
Indirect Data Bit of 31-24 of indirect data R/W 00000000
Register 118 (0x76): Indirect Data Register 2
23−16
Indirect Data Bit 23-16 of indirect data. R/W 00000000
Register 119 (0x77): Indirect Data Register 1
15−8
Indirect Data Bit 15-8 of indirect data. R/W 00000000
Register 120 (0x78): Indirect Data Register 0
7−0
Indirect Data Bit 7-0 of indirect data. R/W 00000000
Register 124 (0x7C): Interrupt Status Register
7–5 Reserved Reserved. RO 000
4 Port 5 Interrupt Status
1, Port 5 interrupt request
0, normal
Note: This bit is set by Port 5 link change. Write a
“1” to clear this bit
RO 0
3 Port 4 Interrupt Status
1, Port 4 interrupt request
0, normal
Note: This bit is set by Port 4 link change. Write a
“1” to clear this bit
RO 0
2 Port 3 Interrupt Status
1, Port 3 interrupt request
0, normal
Note: This bit is set by Port 3 link change. Write a
“1” to clear this bit
RO 0
1 Port 2 Interrupt Status
1, Port 2 interrupt request
0, normal
Note: This bit is set by Port 2 link change. Write a
“1” to clear this bit
RO 0
March 12, 2014
75
Revision 1.7