Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsIntegrated Circuits (ICs)1024 kBit 128 K x 8

 2011 Microchip Technology Inc. Preliminary DS25142A-page 1

23A1024/23LC1024

Device Selection Table

Features:

• SPI-Compatible Bus Interface:

- 20 MHz Clock rate

- SPI/SDI/SQI mode

• Low-Power CMOS Technology:

- Read Current: 3 mA at 5.5V, 20 MHz

- Standby Current: 4 A at +85°C

• Unlimited Read and Write Cycles

• Zero Write Time

• 128K x 8-bit Organization:

- 32-byte page

• Byte, Page and Sequential mode for Reads and

Writes

• High Reliability

• Temperature Range Supported:

• Pb-Free and RoHS Compliant, Halogen Free

• 8 Lead SOIC, TSSOP and PDIP Packages

Pin Function Table

Description:

The Microchip Technology Inc. 23A1024/23LC1024

are 1 Mbit Serial SRAM devices. The memory is

accessed via a simple Serial Peripheral Interface (SPI)

compatible serial bus. The bus signals required are a

clock input (SCK) plus separate data in (SI) and data

out (SO) lines. Access to the device is controlled

through a Chip Select (CS

) input. Additionally, SDI

(Serial Dual Interface) and SQI (Serial Quad Interface)

is supported if your application needs faster data rates.

This device also supports unlimited reads and writes to

the memory array.

The 23A1024/23LC1024 is available in standard

packages including 8-lead SOIC, PDIP and advanced

8-lead TSSOP.

Package Types (not to scale)

Part

Number

CC Range

Dual I/O

(SDI)

Quad I/O

(SQI)

Max Clock

Frequency

Packages

23A1024 1.7-2.2V Yes Yes 20 MHz SN, ST, P

23LC1024 2.5-5.5V Yes Yes 20 MHz SN, ST, P

- Industrial (I): -40Cto +85C

Name Function

Chip Select Input

SO/SIO1 Serial Output/SDI/SQI Pin

SIO2 SQI Pin

Vss Ground

SI/SIO0 Serial Input/SDI/SQI Pin

SCK Serial Clock

HOLD

/SIO3 Hold/SQI Pin

Vcc Power Supply

SO/SIO1

SIO2

Vss

Vcc

HOLD

/SIO3

SCK

SI/SIO0

SOIC/TSSOP/PDIP

1Mbit SPI Serial SRAM with SDI and SQI Interface

Summary of content (32 pages)

PAGE 1
23A1024/23LC1024 1Mbit SPI Serial SRAM with SDI and SQI Interface Device Selection Table Part Number VCC Range Dual I/O (SDI) Quad I/O (SQI) Max Clock Frequency Packages 23A1024 1.7-2.2V Yes Yes 20 MHz SN, ST, P 23LC1024 2.5-5.5V Yes Yes 20 MHz SN, ST, P Features: Description: • SPI-Compatible Bus Interface: - 20 MHz Clock rate - SPI/SDI/SQI mode • Low-Power CMOS Technology: - Read Current: 3 mA at 5.
PAGE 2
3A1024/23LC1024 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +0.3V Storage temperature ........................................................................
PAGE 3
23A1024/23LC1024 TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Param. Sym. No. Industrial (I): Characteristic TA = -40°C to +85°C Min. Max.
PAGE 4
23A1024/23LC1024 FIGURE 1-1: HOLD TIMING CS 16 15 16 15 SCK 17 SO n+2 SI n+2 n+1 18 High-Impedance n n 5 Don’t Care n+1 n-1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING (SPI MODE) 4 CS 2 11 7 8 3 SCK 5 SI 6 MSB in LSB in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING (SPI MODE) CS 9 3 10 SCK 12 13 SO SI DS25142A-page 4 MSB out 14 LSB out Don’t Care Preliminary  2011 Microchip Technology Inc.
PAGE 5
23A1024/23LC1024 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The 23A1024/23LC1024 is an 1 Mbit Serial SRAM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers.
PAGE 6
23A1024/23LC1024 TABLE 2-1: INSTRUCTION SET Instruction Format Hex Code Description READ 0000 0011 0x03 Read data from memory array beginning at selected address WRITE 0000 0010 0x02 Write data to memory array beginning at selected address EDIO 0011 1011 0x3B Enter Dual I/O access Instruction Name EQIO 0011 1000 0x38 Enter Quad I/O access RSTIO 1111 1111 0xFF Reset Dual and Quad I/O access RDMR 0000 0101 0x05 Read Mode Register WRMR 0000 0001 0x01 Write Mode Register FIGURE
PAGE 7
23A1024/23LC1024 FIGURE 2-3: PAGE READ SEQUENCE (SPI MODE) CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction SI 0 0 24-bit Address 0 1 2 1 23 22 21 20 1 0 Page X, Word Y Page X, Word Y High Impedance SO 7 6 5 4 3 2 1 0 CS 40 41 42 43 44 45 46 47 SCK SI Page X, Word Y+1 7 SO 6 FIGURE 2-4: 5 4 3 2 1 Page X, Word 31 0 7 6 5 4 3 2 Page X, Word 0 1 0 7 6 5 4 3 2 1 0 PAGE WRITE SEQUENCE (SPI MODE) CS 0 1 2 0 0 0
PAGE 8
23A1024/23LC1024 FIGURE 2-5: SEQUENTIAL READ SEQUENCE (SPI MODE) CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction SI 0 0 24-bit Address 0 1 1 23 22 21 20 2 1 0 Page X, Word Y 7 SO 6 5 4 3 2 1 0 CS SCK SI Page X, Word 31 SO 7 6 5 4 3 2 Page X+1, Word 0 1 0 7 6 5 4 3 2 1 Page X+1, Word 1 0 7 6 5 4 3 2 1 0 CS SCK SI Page X+1, Word 31 SO 7 DS25142A-page 8 6 5 4 3 2 Page X+n, Word 1 1 0 7 6 5 4 3 2 Preli
PAGE 9
23A1024/23LC1024 FIGURE 2-6: SEQUENTIAL WRITE SEQUENCE (SPI MODE) CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction SI 0 0 0 0 0 24-bit Address 0 1 Data Byte 1 2 0 23 22 21 20 1 0 7 6 5 4 3 2 1 0 CS 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCK Data Byte 2 SI 7 6 5 4  2011 Microchip Technology Inc.
PAGE 10
23A1024/23LC1024 2.5 Read Mode Register Instruction (RDMR) The mode bits indicate the operating mode of the SRAM. The possible modes of operation are: 0 0 = Byte mode The Read Mode Register instruction (RDMR) provides access to the MODE register. The MODE register may be read at any time. The MODE register is formatted as follows: TABLE 2-2: 1 0 = Page mode 0 1 = Sequential mode (default operation) 1 1 = Reserved Bits 0 through 5 are reserved and should always be set to ‘0’.
PAGE 11
23A1024/23LC1024 2.6 Write Mode Register Instruction (WRMR) The Write Mode Register instruction (WRMR) allows the user to write to the bits in the MODE register as shown in Table 2-2. This allows for setting of the Device operating mode. Several of the bits in the MODE register must be cleared to ‘0’. See Figure 2-8 for the WRMR timing sequence.
PAGE 12
23A1024/23LC1024 3.0 PIN DESCRIPTIONS 3.6 The SCK is used to synchronize the communication between a master and the 23A1024/23LC1024. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Name PIN FUNCTION TABLE SOIC/ PDIP TSSOP Function 3.
PAGE 13
23A1024/23LC1024 3.8 SPI/SDI and SQI Pin Designations SPI Mode: CS 1 8 Vcc SO 2 7 HOLD NC 3 6 SCK Vss 4 5 SI SDI Mode: CS 1 8 Vcc SIO1 2 7 HOLD NC 3 6 SCK Vss 4 5 SIO0 SQI Mode: Note: CS 1 8 Vcc SIO1 2 7 SIO3 SIO2 3 6 SCK Vss 4 5 SIO0 Pin 3 should not be left floating when not using SQI Operation.  2011 Microchip Technology Inc.
PAGE 14
23A1024/23LC1024 4.0 DUAL AND QUAD SERIAL MODE 4.1 The 23A1024/23LC1024 supports Serial Dual Input (SDI) mode of operation. To enter SDI mode the EDIO command must be clocked in (Figure 4-1). It should be noted that if the MCU resets before the SRAM, the user will need to determine the serial mode of operation of the SRAM and reset it accordingly. Byte read and write sequence in SDI mode is shown in Figure 4-2 and Figure 4-3.
PAGE 15
23A1024/23LC1024 FIGURE 4-2: BYTE READ MODE SDI CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK 0 SIO0 0 1 22 20 18 16 14 12 10 8 0 0 2 6 Dummy Byte 0 1 23 21 19 17 15 13 11 9 0 0 4 24-Bit Address Instruction SIO1 6 7 5 1 3 4 2 0 Data Out 7 5 3 1 Note: Page and Sequential mode are similar in that additional bytes can be clocked out before CS is brought high. Note: The first byte read after the address will be a dummy byte.
PAGE 16
23A1024/23LC1024 FIGURE 4-4: ENTER SQI MODE (EQIO) FROM SPI MODE CS 0 1 2 3 4 5 6 7 SCK 0 SI 0 1 1 1 0 0 0 High Impedance SO 4.3 Exit SDI or SQI Mode To exit from SDI mode, the RSTIO command must be issued. The command must be entered in the current device configuration, either SDI or SQI, see Figure 4-7 and Figure 4-8.
PAGE 17
23A1024/23LC1024 FIGURE 4-6: BYTE WRITE MODE SQI CS 0 1 2 3 4 5 6 7 8 9 SCK 0 SIO0 SIO1 SIO2 SIO3 Note: 0 20 16 12 8 4 0 4 0 0 1 21 17 13 9 5 1 5 1 0 0 22 18 14 10 6 2 6 2 0 0 23 19 15 11 7 3 7 3 24-Bit Address Instruction Data In Page and Sequential mode are similar in that additional bytes can be clocked out before CS is brought high.
PAGE 18
23A1024/23LC1024 FIGURE 4-8: RESET SDI/SQI MODE (RSTIO) – FROM SQI MODE CS 0 1 SCK DS25142A-page 18 SIO0 1 1 SIO1 1 1 SIO2 1 1 SIO3 1 1 Preliminary  2011 Microchip Technology Inc.
PAGE 19
23A1024/23LC1024 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 8-Lead PDIP (300 mil) Example XXXXXXXX XXXXXNNN 23A1024 I/P e3 1L7 YYWW 0528 8-Lead SOIC (3.90 mm) Example: XXXXXXXT XXXXYYWW NNN 23A1024I SN e3 0528 1L7 Example: 8-Lead TSSOP 3ABI XXXX TYWW NNN Legend: XX...
PAGE 20
23A1024/23LC1024 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6 &! ' ! 9 ' &! 7"') % ! 7,8. 7 7 & ; < & & 7: 1 , = = - 1 ! & & = = .
PAGE 21
23A1024/23LC1024 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc.
PAGE 22
23A1024/23LC1024 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25142A-page 22 Preliminary  2011 Microchip Technology Inc.
PAGE 23
A1024/23LC1024 ! "" #$ %& ! ' 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4  2011 Microchip Technology Inc.
PAGE 24
23A1024/23LC1024 () )" * ! ( +%+ ( ! 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 NOTE 1 1 2 b e c A φ A2 A1 L L1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; < & : 8 & = = < = # # 4 4 !! & # %% ? 1 , : > #& . # # 4 > #& .
PAGE 25
23A1024/23LC1024 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc.
PAGE 26
23A1024/23LC1024 APPENDIX A: REVISION HISTORY Revision A (July 2012) Initial release. DS25142A-page 26 Preliminary  2011 Microchip Technology Inc.
PAGE 27
23A1024/23LC1024 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PAGE 28
23A1024/23LC1024 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PAGE 29
23A1024/23LC1024 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not all possible ordering options are shown below.. PART NO. X Device Tape & Reel – X /XX Temp Range Package Examples: a) b) Device: 23A1024 = 23LC1024 = 1 Mbit, 1.7 - 2.2V, SPI Serial SRAM 1 Mbit, 2.5 - 5.
PAGE 30
23A1024/23LC1024 NOTES: DS25142A-page 30 Preliminary  2012 Microchip Technology Inc.
PAGE 31
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 32
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