Datasheet

AT32UC3A

When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if

CPOL=1 and CPHA=0.

4. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first

transfer

In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or

during the first transfer.

Fix/Workaround

1. Set slave mode, set required CPOL/CPHA.

2. Enable SPI.

3. Set the polarity CPOL of the line in the opposite value of the required one.

4. Set the polarity CPOL to the required one.

5. Read the RXHOLDING register.

Transfers can now befin and RXREADY will now behave as expected.

5. SPI Disable does not work in Slave mode

Fix/workaround

Read the last received data then perform a Software reset.

15.3.4 Power Manager

1. If the BOD level is higher than VDDCORE, the part is constantly under reset

If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will

be in constant reset.

Fix/Workaround

Apply an external voltage on VDDCORE that is higher than the BOD level and is lower than

VDDCORE max and disable the BOD.

15.3.5 Flashc

1. On AT32UC3A0512 and AT32UC3A1512, corrupted read in flash after FLASHC WP,

EP, EA, WUP, EUP commands may happen

- After a FLASHC Write Page (WP) or Erase Page (EP) command applied to a page in a

given half of the flash (first or last 256 kB of flash), reading (data read or code fetch) the

other half of the flash may fail. This may lead to an exception or to other errors derived from

this corrupted read access.

- After a FLASHC Erase All (EA) command, reading (data read or code fetch) the flash may

fail. This may lead to an exception or to other errors derived from this corrupted read access.

- After a FLASHC Write User Page (WUP) or Erase User Page (EUP) command, reading

(data read or code fetch) the second half (last 256 kB) of the flash may fail. This may lead to

an exception or to other errors derived from this corrupted read access.

Fix/Workaround

Flashc WP, EP, EA, WUP, EUP commands: these commands must be issued from RAM or

through the EBI. After these commands, read twice one flash page initialized to 00h in each

half part of the flash.

15.3.6 PDCA

1. Wrong PDCA behavior when using two PDCA channels with the same PID.

32058KS–AVR32–01/12