Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 100 (14x14) 32-Bit 66 MHz I/O number 69

Features

• High Performance, Low Power 32-Bit Atmel

AVR

Microcontroller

– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set

– Read-Modify-Write Instructions and Atomic Bit Manipulation

– Performing 1.49 DMIPS / MHz

Up to 91 DMIPS Running at 66 MHz from Flash (1 Wait-State)

Up to 49 DMIPS Running at 33MHz from Flash (0 Wait-State)

– Memory Protection Unit

• Multi-hierarchy Bus System

– High-Performance Data Transfers on Separate Buses for Increased Performance

– 15 Peripheral DMA Channels Improves Speed for Peripheral Communication

• Internal High-Speed Flash

– 512K Bytes, 256K Bytes, 128K Bytes Versions

– Single Cycle Access up to 33 MHz

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 4ms Page Programming Time and 8ms Full-Chip Erase Time

– 100,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User Defined Configuration Area

• Internal High-Speed SRAM, Single-Cycle Access at Full Speed

– 64K Bytes (512KB and 256KB Flash), 32K Bytes (128KB Flash)

• External Memory Interface on AT32UC3A0 Derivatives

– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)

• Interrupt Controller

– Autovectored Low Latency Interrupt Service with Programmable Priority

• System Functions

– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator

– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing

Independant CPU Frequency from USB Frequency

– Watchdog Timer, Real-Time Clock Timer

• Universal Serial Bus (USB)

– Device 2.0 Full Speed and On-The-Go (OTG) Low Speed and Full Speed

– Flexible End-Point Configuration and Management with Dedicated DMA Channels

– On-chip Transceivers Including Pull-Ups

• Ethernet MAC 10/100 Mbps interface

– 802.3 Ethernet Media Access Controller

– Supports Media Independent Interface (MII) and Reduced MII (RMII)

• One Three-Channel 16-bit Timer/Counter (TC)

– Three External Clock Inputs, PWM, Capture and Various Counting Capabilities

• One 7-Channel 16-bit Pulse Width Modulation Controller (PWM)

• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces

– Support for Hardware Handshaking, RS485 Interfaces and Modem Line

• Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals

• One Synchronous Serial Protocol Controller

– Supports I2S and Generic Frame-Based Protocols

• One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible

• One 8-channel 10-bit Analog-To-Digital Converter

• 16-bit Stereo Audio Bitstream

– Sample Rate Up to 50 KHz

32-Bit Atmel AVR

Microcontroller

AT32UC3A0512

AT32UC3A0256

AT32UC3A0128

AT32UC3A1512

AT32UC3A1256

AT32UC3A1128

Summary

32058KS–AVR32–01/12

Summary of content (98 pages)

PAGE 1
Features • High Performance, Low Power 32-Bit Atmel® AVR® Microcontroller • • • • • • • • • • • • • • • • – Compact Single-cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performing 1.
PAGE 2
AT32UC3A • On-Chip Debug System (JTAG interface) – Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace • 100-pin TQFP (69 GPIO pins), 144-pin LQFP (109 GPIO pins) , 144 BGA (109 GPIO pins) • 5V Input Tolerant I/Os • Single 3.3V Power Supply or Dual 1.8V-3.
PAGE 3
AT32UC3A 1. Description The AT32UC3A is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 66 MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance.
PAGE 4
AT32UC3A 2. Configuration Summary The table below lists all AT32UC3A memory and package configurations: Device Flash SRAM Ext.
PAGE 5
AT32UC3A 4. Blockdiagram Blockdiagram M DC , TXD [3..0], TX_C LK, TX_EN , TX_ER , SPEED DM A S M DM A M M M M HIG H SPEED BUS M ATRIX S S ETHERNET M AC M S C ON FIGU RATIO N PB HS B HSB-PB BRIDG E B M D IO REG ISTER S BUS H SB PERIPHERAL DM A CO NTRO LLER HSB-PB BRIDG E A PB XIN 32 XO UT32 XIN0 XO U T0 XIN1 XO U T1 32 KHz O SC CLO CK G ENERATO R O SC0 O SC1 PLL0 PDC PO W ER M ANAG ER SD A10 SD CK SDC KE SD CS0 SD W E PDC 115 kHz RCO SC NC S[3..
PAGE 6
AT32UC3A 4.1 4.1.1 Processor and architecture AVR32 UC CPU • 32-bit load/store AVR32A RISC architecture. – – – – – 15 general-purpose 32-bit registers. 32-bit Stack Pointer, Program Counter and Link Register reside in register file. Fully orthogonal instruction set. Privileged and unprivileged modes enabling efficient and secure Operating Systems. Innovative instruction set together with variable instruction length ensuring industry leading code density.
PAGE 7
AT32UC3A • Peripheral Bus A able to run on at divided bus speeds compared to the High Speed Bus Figure 4-1 gives an overview of the bus system. All modules connected to the same bus use the same clock, but the clock to each module can be individually shut off by the Power Manager. The figure identifies the number of master and slave interfaces of each module connected to the High Speed Bus, and which DMA controller is connected to which peripheral.
PAGE 8
AT32UC3A 5. Signals Description The following table gives details on the signal name classified by peripheral The signals are multiplexed with GPIO pins as described in ”Peripheral Multiplexing on I/O lines” on page 31. Table 5-1. Signal Description List Signal Name Function Type Active Level Comments Power VDDPLL Power supply for PLL Power Input 1.65V to 1.95 V VDDCORE Core Power Supply Power Input 1.65V to 1.95 V VDDIO I/O Power Supply Power Input 3.0V to 3.
PAGE 9
AT32UC3A Table 5-1.
PAGE 10
AT32UC3A Table 5-1.
PAGE 11
AT32UC3A Table 5-1.
PAGE 12
AT32UC3A Table 5-1. Signal Description List Signal Name Function Type Active Level Comments Analog to Digital Converter - ADC AD0 - AD7 Analog input pins Analog input ADVREF Analog positive reference voltage input Analog input 2.6 to 3.
PAGE 13
AT32UC3A 6. Package and Pinout The device pins are multiplexed with peripheral functions as described in ”Peripheral Multiplexing on I/O lines” on page 31. Figure 6-1. TQFP100 Pinout 75 51 76 50 100 26 1 Table 6-1.
PAGE 14
AT32UC3A Table 6-1. TQFP100 Package Pinout 23 PA02 48 DM 73 PB05 98 PB17 24 PA03 49 DP 74 PB06 99 PB18 25 PA04 50 GND 75 PB07 100 PB19 Figure 6-2. LQFP144 Pinout 108 73 109 72 144 37 1 Table 6-2.
PAGE 15
AT32UC3A Table 6-2.
PAGE 16
AT32UC3A Table 6-3. BGA144 Package Pinout A1..
PAGE 17
AT32UC3A 7. Power Considerations 7.1 Power Supplies The AT32UC3A has several types of power supply pins: • • • • • VDDIO: Powers I/O lines. Voltage is 3.3V nominal. VDDANA: Powers the ADC Voltage is 3.3V nominal. VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal. VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal. VDDPLL: Powers the PLL. Voltage is 1.8V nominal. The ground pins GND are common to VDDCORE, VDDIO, VDDPLL. The ground pin for VDDANA is GNDANA.
PAGE 18
AT32UC3A 7.2 7.2.1 Voltage Regulator Single Power Supply The AT32UC3A embeds a voltage regulator that converts from 3.3V to 1.8V. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDOUT. VDDOUT should be externally connected to the 1.8V domains. Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. Two input decoupling capacitors must be placed close to the chip.
PAGE 19
AT32UC3A 7.3 Analog-to-Digital Converter (A.D.C) reference. The ADC reference (ADVREF) must be provided from an external source. Two decoupling capacitors must be used to insure proper decoupling. 3.3V ADVREF C VREF2 C VREF1 Refer to Section 12.4 on page 42 for decoupling capacitors values and electrical characteristics. In case ADC is not used, the ADVREF pin should be connected to GND to avoid extra consumption.
PAGE 20
AT32UC3A 8. I/O Line Considerations 8.1 JTAG pins TMS, TDI and TCK have pull-up resistors. TDO is an output, driven at up to VDDIO, and has no pull-up resistor. 8.2 RESET_N pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. 8.
PAGE 21
AT32UC3A 9. Memories 9.
PAGE 22
AT32UC3A Table 9-2. 9.
PAGE 23
AT32UC3A Figure 9-1.
PAGE 24
AT32UC3A 10. Peripherals 10.1 Peripheral address map Table 10-1.
PAGE 25
AT32UC3A Table 10-1. Peripheral Address Mapping (Continued) Address 0xFFFF1C00 0xFFFF2000 0xFFFF2400 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 0xFFFF3C00 10.
PAGE 26
AT32UC3A The following GPIO registers are mapped on the local bus: Table 10-2.
PAGE 27
AT32UC3A Table 10-2. Local bus mapped GPIO registers Port Register Mode Local Bus Address Access 3 Output Driver Enable Register (ODER) WRITE 0x4000_0340 Write-only SET 0x4000_0344 Write-only CLEAR 0x4000_0348 Write-only TOGGLE 0x4000_034C Write-only WRITE 0x4000_0350 Write-only SET 0x4000_0354 Write-only CLEAR 0x4000_0358 Write-only TOGGLE 0x4000_035C Write-only - 0x4000_0360 Read-only Output Value Register (OVR) Pin Value Register (PVR) 10.
PAGE 28
AT32UC3A Table 10-3.
PAGE 29
AT32UC3A Table 10-3. Interrupt Request Signal Map 9 0 Serial Peripheral Interface SPI0 10 0 Serial Peripheral Interface SPI1 11 0 Two-wire Interface TWI 12 0 Pulse Width Modulation Controller PWM 13 0 Synchronous Serial Controller SSC 0 Timer/Counter TC0 1 Timer/Counter TC1 2 Timer/Counter TC2 15 0 Analog to Digital Converter ADC 16 0 Ethernet MAC MACB 17 0 USB 2.0 OTG Interface USBB 18 0 SDRAM Controller 19 0 Audio Bitstream DAC 14 10.4 10.4.
PAGE 30
AT32UC3A 10.4.3 SPIs Each SPI can be connected to an internally divided clock: Table 10-6. SPI clock connections SPI Source Name Connection 0 Internal CLK_DIV PBA clock or PBA clock / 32 1 10.5 Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespectively of the PIO configuration. Two different OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register.
PAGE 31
AT32UC3A Table 10-8. 10.7 PDC Handshake Signals PID Value Peripheral module & direction 4 USART2 - RX 5 USART3 - RX 6 TWI - RX 7 SPI0 - RX 8 SPI1 - RX 9 SSC - TX 10 USART0 - TX 11 USART1 - TX 12 USART2 - TX 13 USART3 - TX 14 TWI - TX 15 SPI0 - TX 16 SPI1 - TX 17 ABDAC Peripheral Multiplexing on I/O lines Each GPIO line can be assigned to one of 3 peripheral functions; A, B or C.
PAGE 32
AT32UC3A Table 10-9.
PAGE 33
AT32UC3A Table 10-9.
PAGE 34
AT32UC3A Table 10-9. 10.
PAGE 35
AT32UC3A 10.10 GPIO The GPIO open drain feature (GPIO ODMER register (Open Drain Mode Enable Register)) is not available for this device. 10.11 Peripheral overview 10.11.
PAGE 36
AT32UC3A – Supports Mobile SDRAM Devices • Error Detection – Refresh Error Interrupt • SDRAM Power-up Initialization by Software • CAS Latency of 1, 2, 3 Supported • Auto Precharge Command Not Used 10.11.4 USB Controller 10.11.5 • USB 2.
PAGE 37
AT32UC3A – Optional Manchester Encoding • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication at up to 115.
PAGE 38
AT32UC3A 10.11.11 Ethernet 10/100 MAC • • • • • • • • • • • • Compatibility with IEEE Standard 802.
PAGE 39
AT32UC3A 11. Boot Sequence This chapter summarizes the boot sequence of the AT32UC3A. The behaviour after power-up is controlled by the Power Manager. For specific details, refer to Section 13. ”Power Manager (PM)” on page 53. 11.1 Starting of clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device. Once the power has stabilized, the device will use the internal RC Oscillator as clock source.
PAGE 40
AT32UC3A 12. Electrical Characteristics 12.1 Absolute Maximum Ratings* Operating Temperature......................................-40⋅C to +85⋅C Storage Temperature ..................................... -60°C to +150°C Voltage on Input Pin with respect to Ground except for PC00, PC01, PC02, PC03, PC04, PC05..........................................................-0.3V to 5.5V Voltage on Input Pin with respect to Ground for PC00, PC01, PC02, PC03, PC04, PC05................................................
PAGE 41
AT32UC3A 12.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise specified and are certified for a junction temperature up to TJ = 100°C. Table 12-1. DC Characteristics Symbol Parameter VVDDCOR DC Supply Core VVDDPLL Condition Min. Typ. Max Units 1.65 1.95 V DC Supply PLL 1.65 1.95 V VVDDIO DC Supply Peripheral I/Os 3.0 3.6 V VREF Analog reference voltage 2.6 3.
PAGE 42
AT32UC3A 12.3 Regulator characteristics Table 12-2. Symbol Parameter VVDDIN Supply voltage (input) VVDDOUT Supply voltage (output) IOUT ISCR Electrical characteristics Condition Min. Typ. Max. Units 3 3.3 3.6 V 1.81 1.85 1.89 V Maximum DC output current with VVDDIN = 3.3V 100 mA Maximum DC output current with VVDDIN = 2.7V 90 mA Low Power mode (stop, deep stop or static) at TA =25°C Static Current of internal regulator Table 12-3.
PAGE 43
AT32UC3A Table 12-7. 12.4.2 BOD Timing Symbol Parameter Test Conditions Typ. Max. Units. TBOD Minimum time with VDDCORE < VBOD to detect power failure Falling VDDCORE from 1.8V to 1.1V 300 800 ns POR Table 12-8. Electrical Characteristic Symbol Parameter Test Conditions VDDRR VDDCORE rise rate to ensure power-on-reset 0.01 VSSFR VDDCORE fall rate to ensure power-on-reset 0.
PAGE 44
AT32UC3A 12.5 Power Consumption The values in Table 12-9 and Table 12-10 on page 46 are measured values of power consumption with operating conditions as follows: •VDDIO = 3.3V •VDDCORE = VDDPLL = 1.8V •TA = 25°C, TA = 85°C •I/Os are configured in input, pull-up enabled. Figure 12-1.
PAGE 45
AT32UC3A These figures represent the power consumption measured on the power supplies. Table 12-9. Power Consumption for Different Modes Mode Conditions Active Typ : Ta =25 °C CPU running from flash (1). VDDIN=3.3 V. VDDCORE =1.8V. CPU clocked from PLL0 at f MHz Voltage regulator is on. XIN0 : external clock. (1) XIN1 stopped. XIN32 stopped PLL0 running All peripheral clocks activated. GPIOs on internal pull-up. JTAG unconnected with ext pull-up. Idle Frozen Standby Typ.
PAGE 46
AT32UC3A Table 12-9. Power Consumption for Different Modes Mode Conditions Stop Typ : Ta = 25 °C. CPU is in stop mode GPIOs on internal pull-up. All peripheral clocks de-activated. DM and DP pins connected to ground. XIN0,Xin1 and XIN2 are stopped Deepstop Static 1. Typ. Unit on Amp0 47 uA on Amp1 40 uA Typ : Ta = 25 °C.CPU is in deepstop mode GPIOs on internal pull-up. All peripheral clocks de-activated. DM and DP pins connected to ground.
PAGE 47
AT32UC3A • VDDCORE = 1.8V • Ambient Temperature = 25°C 12.6.1 CPU/HSB Clock Characteristics Table 12-11. Core Clock Waveform Parameters Symbol Parameter 1/(tCPCPU) CPU Clock Frequency tCPCPU CPU Clock Period 12.6.2 Conditions Min Max Units 66 MHz 15,15 ns PBA Clock Characteristics Table 12-12. PBA Clock Waveform Parameters Symbol Parameter 1/(tCPPBA) PBA Clock Frequency tCPPBA PBA Clock Period 12.6.
PAGE 48
AT32UC3A 12.7.2 Main Oscillators Characteristics Table 12-15. Main Oscillator Characteristics Symbol Parameter 1/(tCPMAIN) Crystal Oscillator Frequency CL1, CL2 Internal Load Capacitance (CL1 = CL2) Conditions Min Typ 0.45 Unit 16 MHz 12 Duty Cycle 40 tST Startup Time 1/(tCPXIN) XIN Clock Frequency tCHXIN XIN Clock High Half-period 0.4 x tCPXIN tCLXIN XIN Clock Low Half-period 0.4 x tCPXIN CIN XIN Input Capacitance 50 External clock 12.7.3 Max Crystal 0.
PAGE 49
AT32UC3A 12.8 ADC Characteristics Table 12-17. Channel Conversion Time and ADC Clock Parameter Conditions ADC Clock Frequency ADC Clock Frequency Startup Time Min Max Units 10-bit resolution mode 5 MHz 8-bit resolution mode 8 MHz Return from Idle Mode 20 µs Track and Hold Acquisition Time Typ 600 Conversion Time ADC Clock = 5 MHz ns 2 µs Conversion Time ADC Clock = 8 MHz 1.
PAGE 50
AT32UC3A Table 12-21. Transfer Characteristics in 10-bit mode Parameter Conditions Min Resolution Typ Max 10 Units Bit Absolute Accuracy f=5MHz Integral Non-linearity f=5MHz 1.5 2 LSB f=5MHz 1 2 LSB 0.6 1 LSB Differential Non-linearity 3 f=2.
PAGE 51
AT32UC3A 12.9 EBI Timings These timings are given for worst case process, T = 85⋅C, VDDCORE = 1.65V, VDDIO = 3V and 40 pF load capacitance. Table 12-22. SMC Clock Signal. Symbol Parameter 1/(tCPSMC) SMC Controller Clock Frequency Note: Max(1) Units 1/(tcpcpu) MHz 1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB. Table 12-23.
PAGE 52
AT32UC3A Table 12-24. SMC Read Signals with no Hold Settings Symbol Parameter Min Units NRD Controlled (READ_MODE = 1) SMC19 Data Setup before NRD High SMC20 Data Hold after NRD High 13.7 ns 1 NRD Controlled (READ_MODE = 0) SMC21 Data Setup before NCS High SMC22 Data Hold after NCS High 13.3 ns 0 Table 12-25. SMC Write Signals with Hold Settings Symbol Parameter Min Units NRD Controlled (READ_MODE = 1) SMC23 Data Out Valid before NWE High (nwe pulse length - 1) * tCPSMC - 0.
PAGE 53
AT32UC3A Table 12-26. SMC Write Signals with No Hold Settings (NWE Controlled only). Symbol Parameter Min SMC37 NWE Rising to A2-A25 Valid 5.4 SMC38 NWE Rising to NBS0/A0 Valid 5 SMC39 NWE Rising to NBS1 Change 5 SMC40 NWE Rising to A1/NBS2 Change 5 SMC41 NWE Rising to NBS3 Change 5 SMC42 NWE Rising to NCS Rising SMC43 Data Out Valid before NWE Rising SMC44 Data Out Valid after NWE Rising SMC45 NWE Pulse Width Units ns 5.1 (nwe pulse length - 1) * tCPSMC - 1.
PAGE 54
AT32UC3A Figure 12-3. SMC Signals for NRD and NRW Controlled Accesses. SMC37 SMC7 SMC7 SMC31 A2-A25 SMC25 SMC26 SMC29 SMC30 SMC3 SMC4 SMC5 SMC6 SMC38 SMC39 SMC40 SMC41 SMC3 SMC4 SMC5 SMC6 A0/A1/NBS[3:0] SMC42 SMC32 SMC8 NCS SMC8 SMC9 SMC9 NRD SMC19 SMC20 SMC43 SMC44 SMC1 SMC23 SMC2 SMC24 D0 - D15 SMC45 SMC33 NWE 12.9.1 SDRAM Signals These timings are given for 10 pF load on SDCK and 40 pF on other signals. Table 12-27. SDRAM Clock Signal.
PAGE 55
AT32UC3A Table 12-28. SDRAM Clock Signal. Symbol Parameter Min SDRAMC11 Address Change before SDCK Rising Edge 6.2 SDRAMC12 Address Change after SDCK Rising Edge 2.2 SDRAMC13 Bank Change before SDCK Rising Edge 6.3 SDRAMC14 Bank Change after SDCK Rising Edge 2.4 SDRAMC15 CAS Low before SDCK Rising Edge 7.4 SDRAMC16 CAS High after SDCK Rising Edge 1.9 SDRAMC17 DQM Change before SDCK Rising Edge 6.4 SDRAMC18 DQM Change after SDCK Rising Edge 2.
PAGE 56
AT32UC3A Figure 12-4. SDRAMC Signals relative to SDCK.
PAGE 57
AT32UC3A 12.10 JTAG Timings 12.10.1 JTAG Interface Signals Table 12-29.
PAGE 58
AT32UC3A Figure 12-5. JTAG Interface Signals JTAG2 TCK JTAG JTAG1 0 TMS/TDI JTAG3 JTAG4 JTAG7 JTAG8 TDO JTAG5 JTAG6 Device Inputs Device Outputs JTAG9 JTAG10 12.11 SPI Characteristics Figure 12-6.
PAGE 59
AT32UC3A Figure 12-7. SPI Master mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK SPI3 SPI4 MISO SPI5 MOSI Figure 12-8. SPI Slave mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK SPI6 MISO SPI7 SPI8 MOSI Figure 12-9.
PAGE 60
AT32UC3A Table 12-30. SPI Timings Symbol SPI0 Parameter MISO Setup time before SPCK rises (master) SPI1 MISO Hold time after SPCK rises (master) SPI2 SPCK rising to MOSI Delay (master) Conditions (1) 3.3V domain 3.3V domain (1) (1) 3.3V domain SPI4 MISO Hold time after SPCK falls (master) 3.3V domain (1) SPI5 SPCK falling to MOSI Delay (master) 3.
PAGE 61
AT32UC3A Table 12-32. Ethernet MAC MII Specific Signals Symbol EMAC12 EMAC13 Parameter Conditions Hold for ERX from ERXCK Setup for ERXER from ERXCK Min (ns) Load: 20pF (1) 1.5 Load: 20pF (1) 1 (1) 0.5 EMAC14 Hold for ERXER from ERXCK Load: 20pF EMAC15 Setup for ERXDV from ERXCK Load: 20pF (1) 1.5 EMAC16 Hold for ERXDV from ERXCK Load: 20pF (1) 1 Note: Max (ns) 1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 20 pF Figure 12-10.
PAGE 62
AT32UC3A Table 12-33. Ethernet MAC RMII Specific Signals Symbol Parameter Min (ns) Max (ns) EMAC21 ETXEN toggling from EREFCK rising 7 14.5 EMAC22 ETX toggling from EREFCK rising 7 14.7 EMAC23 Setup for ERX from EREFCK 1.5 EMAC24 Hold for ERX from EREFCK 0 EMAC25 Setup for ERXER from EREFCK 1.5 EMAC26 Hold for ERXER from EREFCK 0 EMAC27 Setup for ECRSDV from EREFCK 1.5 EMAC28 Hold for ECRSDV from EREFCK 0 Figure 12-11.
PAGE 63
AT32UC3A Table 12-35.
PAGE 64
AT32UC3A 13. Mechanical Characteristics 13.1 13.1.1 Thermal Considerations Thermal Data Table 13-1 summarizes the thermal resistance data depending on the package. Table 13-1. 13.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ θJA Junction-to-ambient thermal resistance Still Air TQFP100 43.4 θJC Junction-to-case thermal resistance TQFP100 5.5 θJA Junction-to-ambient thermal resistance LQFP144 39.8 θJC Junction-to-case thermal resistance LQFP144 8.
PAGE 65
AT32UC3A 13.2 Package Drawings Figure 13-1. TQFP-100 package drawing Table 13-2. Device and Package Maximum Weight 500 Table 13-3. mg Package Characteristics Moisture Sensitivity Level Table 13-4.
PAGE 66
AT32UC3A Figure 13-2. LQFP-144 package drawing Table 13-5. Device and Package Maximum Weight 1300 Table 13-6. mg Package Characteristics Moisture Sensitivity Level Table 13-7.
PAGE 67
AT32UC3A Figure 13-3. FFBGA-144 package drawing Table 13-8. Device and Package Maximum Weight 1300 Table 13-9. mg Package Characteristics Moisture Sensitivity Level MSL3 Table 13-10.
PAGE 68
AT32UC3A 13.3 Soldering Profile Table 13-11 gives the recommended soldering profile from J-STD-20. Table 13-11. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/sec Preheat Temperature 175°C ±25°C Min. 150 °C, Max. 200 °C Time Maintained Above 217°C 60-150 sec Time within 5⋅C of Actual Peak Temperature 30 sec Peak Temperature Range 260 °C Ramp-down Rate 6 °C/sec Time 25⋅C to Peak Temperature Max.
PAGE 69
AT32UC3A 14. Ordering Information Table 14-1. Ordering Information Device AT32UC3A0512 AT32UC3A0256 AT32UC3A0128 AT32UC3A1512 AT32UC3A1256 AT32UC3A1128 14.
PAGE 70
AT32UC3A 15. Errata All industrial parts labelled with -UES (engineering samples) are revision E parts. 15.1 15.1.1 Rev. K, L, M PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2.
PAGE 71
AT32UC3A 3. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and NCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK. Fix/workaround When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 4.
PAGE 72
AT32UC3A For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. Fix/Workaround None.
PAGE 73
AT32UC3A 15.2 15.2.1 Rev. J PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. PWM counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle.
PAGE 74
AT32UC3A When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 4. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first transfer In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or during the first transfer. Fix/Workaround 1. Set slave mode, set required CPOL/CPHA. 2. Enable SPI. 3. Set the polarity CPOL of the line in the opposite value of the required one. 4.
PAGE 75
AT32UC3A None. 15.2.9 USART 15.2.10 1. ISO7816 info register US_NER cannot be read The NER register always returns zero. Fix/Workaround None Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12.
PAGE 76
AT32UC3A 15.3 15.3.1 Rev. I PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. PWM counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle.
PAGE 77
AT32UC3A When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 4. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first transfer In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or during the first transfer. Fix/Workaround 1. Set slave mode, set required CPOL/CPHA. 2. Enable SPI. 3. Set the polarity CPOL of the line in the opposite value of the required one. 4.
PAGE 78
AT32UC3A Workaround/fix The same PID should not be assigned to more than one channel. 15.3.7 GPIO 1. Some GPIO VIH (input high voltage) are 3.6V max instead of 5V tolerant Only 11 GPIOs remain 5V tolerant (VIHmax=5V):PB01, PB02, PB03, PB10, PB19, PB20, PB21, PB22, PB23, PB27, PB28. Workaround/fix None. 15.3.8 USART 1. ISO7816 info register US_NER cannot be read The NER register always returns zero. Fix/Workaround None. 15.3.9 TWI 1.
PAGE 79
AT32UC3A specific case. 2. Execute the RETE instruction.
PAGE 80
AT32UC3A 15.4 15.4.1 Rev. H PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. PWM counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle.
PAGE 81
AT32UC3A 4. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and NCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK. Fix/workaround When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 5.
PAGE 82
AT32UC3A (data read or code fetch) the second half (last 256 kB) of the flash may fail. This may lead to an exception or to other errors derived from this corrupted read access. Fix/Workaround Flashc WP, EP, EA, WUP, EUP commands: these commands must be issued from RAM or through the EBI. After these commands, read twice one flash page initialized to 00h in each half part of the flash. 15.4.6 PDCA 1. Wrong PDCA behavior when using two PDCA channels with the same PID.
PAGE 83
AT32UC3A RETS behaves incorrectly when MPU is enabled and MPU is configured so that system stack is not readable in unprivileged mode. Fix/Woraround Workaround 1: Make system stack readable in unprivileged mode, or Workaround 2: Return from supervisor mode using rete instead of rets. This requires : 1. Changing the mode bits from 001b to 110b before issuing the instruction. Updating the mode bits to the desired value must be done using a single mtsr instruction so it is done atomically.
PAGE 84
AT32UC3A 15.5 Rev. E 15.5.1 SPI 1. SPI FDIV option does not work Selecting clock signal using FDIV = 1 does not work as specified. Fix/Workaround Do not set FDIV = 1. 2. SPI Slave / PDCA transfer: no TX UNDERRUN flag There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to be informed of a character lost in transmission. Fix/Workaround For PDCA transfer: none. 3.
PAGE 85
AT32UC3A Fix/workaround When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 15.5.2 PWM 1. PWM counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle. Fix/Workaround - The first period is 0x0000, 0x0001, ..., period - Consecutive periods are 0x0001, 0x0002, ..., period 2.
PAGE 86
AT32UC3A 15.5.4 USB 1. USB No end of host reset signaled upon disconnection In host mode, in case of an unexpected device disconnection whereas a usb reset is being sent by the usb controller, the UHCON.RESET bit may not been cleared by the hardware at the end of the reset. Fix/Workaround A software workaround consists in testing (by polling or interrupt) the disconnection (UHINT.DDISCI == 1) while waiting for the end of reset (UHCON.RESET == 0) to avoid being stuck. 2.
PAGE 87
AT32UC3A 6. CPU Cycle Counter does not reset the COUNT system register on COMPARE match. The device revision E does not reset the COUNT system register on COMPARE match. In this revision, the COUNT register is clocked by the CPU clock, so when the CPU clock stops, so does incrementing of COUNT. Fix/Workaround None. 7. Memory Protection Unit (MPU) is non functional. Fix/Workaround Do not use the MPU. 8.
PAGE 88
AT32UC3A 12. CPU cannot operate on a divided slow clock (internal RC oscillator) Fix/Workaround Do not run the CPU on a divided slow clock. 13. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. Fix/Workaround None. 14.
PAGE 89
AT32UC3A 2. USART RXBREAK problem when no timeguard In asynchronous mode the RXBREAK flag is not correctly handled when the timeguard is 0 and the break character is located just after the stop bit. Fix/Workaround If the NBSTOP is 1, timeguard should be different from 0. 3. USART Handshaking: 2 characters sent / CTS rises when TX If CTS switches from 0 to 1 during the TX of a character, if the Holding register is not empty, the TXHOLDING is also transmitted. Fix/Workaround None. 4.
PAGE 90
AT32UC3A Fix/Workaround In PLL0/1 Control register, the bit 7 should be set in order to prevent unexpected behaviour. 4. Peripheral Bus A maximum frequency is 33MHz instead of 66MHz. Fix/Workaround Do not set PBA frequency higher than 33 MHz. 5. PCx pins go low in stop mode In sleep mode stop all PCx pins will be controlled by GPIO module instead of oscillators. This can cause drive contention on the XINx in worst case. Fix/Workaround Before entering stop mode set all PCx pins to input and GPIO controlled.
PAGE 91
AT32UC3A If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion. 15.5.11 ABDAC 1. Audio Bitstream DAC is not functional. Fix/Workaround Do not use the ABDAC on revE. 15.5.12 FLASHC 1. The address of Flash General Purpose Fuse Register Low (FGPFRLO) is 0xFFFE140C on revE instead of 0xFFFE1410. Fix/Workaround None. 2.
PAGE 92
AT32UC3A 2. The RTC CLKEN bit (bit number 16) of CTRL register is not available. Fix/Workaround Do not use the CLKEN bit of the RTC on Rev E. 15.5.14 OCD 1. Stalled memory access instruction writeback fails if followed by a HW breakpoint. Consider the following assembly code sequence: A B If a hardware breakpoint is placed on instruction B, and instruction A is a memory access instruction, register file updates from instruction A can be discarded.
PAGE 93
AT32UC3A 16. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 16.1 16.2 16.3 16.4 16.5 Rev. K – 01/12 1. Update ”Errata” on page 70. 2. Update eletrical characteristic in ”DC Characteristics” on page 41. 3. Remove Preliminary from first page. 1. Update ”Errata” on page 70. 2.
PAGE 94
AT32UC3A 16.6 16.7 16.8 Rev. C – 10/07 1. Updated ”Signal Description List” on page 8. Removed RXDN and TXDN from USART section. 2. Updated ”Errata” on page 70. Rev G replaced by rev H. 1. Updated ”Features” on page 1. 2. Update ”Blockdiagram” on page 4 with local bus. 3. Updated ”Peripherals” on page 34 with local bus. 4. Add SPI feature in ”Universial Synchronous/Asynchronous Receiver/Transmitter (USART)” on page 315. 5. Updated ”USB On-The-Go Interface (USBB)” on page 517. 6.
PAGE 95
AT32UC3A Table of Contents 1 Description ............................................................................................... 3 2 Configuration Summary .......................................................................... 4 3 Abbreviations ........................................................................................... 4 4 Blockdiagram ........................................................................................... 5 4.1Processor and architecture ................
PAGE 96
10.11Peripheral overview .............................................................................................35 11 Boot Sequence ....................................................................................... 39 11.1Starting of clocks ...................................................................................................39 11.2Fetching of initial instructions ................................................................................39 12 Electrical Characteristics ......
PAGE 97
AT32UC3A 16.4Rev. E – 04/08 .......................................................................................................93 16.5Rev. D – 04/08 ......................................................................................................93 16.6Rev. C – 10/07 ......................................................................................................94 16.7Rev. B – 10/07 .......................................................................................................94 16.
PAGE 98
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 16F, Shin Osaki Kangyo Bldg.