Datasheet

92
AT32UC3A
2. The RTC CLKEN bit (bit number 16) of CTRL register is not available.
Fix/Workaround
Do not use the CLKEN bit of the RTC on Rev E.
15.5.14 OCD
1. Stalled memory access instruction writeback fails if followed by a HW breakpoint.
Consider the following assembly code sequence:
A
B
If a hardware breakpoint is placed on instruction B, and instruction A is a memory access
instruction, register file updates from instruction A can be discarded.
Fix/Workaround
Do not place hardware breakpoints, use software breakpoints instead.
Alternatively, place a hardware breakpoint on the instruction before the memory
access instruction and then single step over the memory access instruction.
15.5.15 PDCA
1. Wrong PDCA behavior when using two PDCA channels with the same PID.
Workaround/fix
The same PID should not be assigned to more than one channel.
15.5.16 TWI
1. The TWI RXRDY flag in SR register is not reset when a software reset is performed.
Fix/Workaround
After a Software Reset, the register TWI RHR must be read.
32058KS–AVR32–01/12