Datasheet

32072SH–AVR32–10/2012

AT32UC3A3

4. Processor and Architecture

Rev: 1.4.2.0

This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the

AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre-

sented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical

Reference Manual.

4.1 Features

• 32-bit load/store AVR32A RISC architecture

– 15 general-purpose 32-bit registers

– 32-bit Stack Pointer, Program Counter and Link Register reside in register file

– Fully orthogonal instruction set

– Privileged and unprivileged modes enabling efficient and secure Operating Systems

– Innovative instruction set together with variable instruction length ensuring industry leading

code density

– DSP extention with saturating arithmetic, and a wide variety of multiply instructions

• 3-stage pipeline allows one instruction per clock cycle for most instructions

– Byte, halfword, word and double word memory access

– Multiple interrupt priority levels

• MPU allows for operating systems with memory protection

4.2 AVR32 Architecture

AVR32 is a high-performance 32-bit RISC microprocessor architecture, designed for cost-sensi-

tive embedded applications, with particular emphasis on low power consumption and high code

density. In addition, the instruction set architecture has been tuned to allow a variety of micro-

architectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance

processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications.

Through a quantitative approach, a large set of industry recognized benchmarks has been com-

piled and analyzed to achieve the best code density in its class. In addition to lowering the

memory requirements, a compact code size also contributes to the core’s low power characteris-

tics. The processor supports byte and halfword data types without penalty in code size and

performance.

Memory load and store operations are provided for byte, halfword, word, and double word data

with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely

linked to the architecture and is able to exploit code optimization features, both for size and

speed.

In order to reduce code size to a minimum, some instructions have multiple addressing modes.

As an example, instructions with immediates often have a compact format with a smaller imme-

diate, and an extended format with a larger immediate. In this way, the compiler is able to use

the format giving the smallest code size.

Another feature of the instruction set is that frequently used instructions, like add, have a com-

pact format with two operands as well as an extended format with three operands. The larger

format increases performance, allowing an addition and a data move in the same instruction in a

single cycle. Load and store instructions have several different formats in order to reduce code

size and speed up execution.