Datasheet

34
32072SH–AVR32–10/2012
AT32UC3A3
5. Memories
5.1 Embedded Memories
• Internal High-Speed Flash
– 256KBytes (AT32UC3A3256/S)
– 128Kbytes (AT32UC3A3128/S)
– 64Kbytes (AT32UC3A364/S)
• 0 wait state access at up to 42MHz in worst case conditions
• 1 wait state access at up to 84MHz in worst case conditions
• Pipelined Flash architecture, allowing burst reads from sequential Flash locations, hiding
penalty of 1 wait state access
• Pipelined Flash architecture typically reduces the cycle penalty of 1 wait state operation
to only 15% compared to 0 wait state operation
• 100 000 write cycles, 15-year data retention capability
• Sector lock capabilities, Bootloader protection, Security Bit
• 32 Fuses, Erased During Chip Erase
• User page for data to be preserved during Chip Erase
• Internal High-Speed SRAM
– 64KBytes, Single-cycle access at full speed on CPU Local Bus and accessible through the
High Speed Bud (HSB) matrix
– 2x32KBytes, accessible independently through the High Speed Bud (HSB) matrix
5.2 Physical Memory Map
The System Bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot.
Note that AVR32 UC CPU uses unsegmented translation, as described in the AVR32UC Techni-
cal Architecture Manual.
The 32-bit physical address space is mapped as follows:
Table 5-1. AT32UC3A3A4 Physical Memory Map
Device
Start
Address
Size Size Size
AT32UC3A3256S
AT32UC3A3256
AT32UC3A4256S
AT32UC3A4256
AT32UC3A3128S
AT32UC3A3128
AT32UC3A4128S
AT32UC3A4128
AT32UC3A364S
AT32UC3A364
AT32UC3A464S
AT32UC3A464
Embedded CPU SRAM 0x00000000 64KByte 64KByte 64KByte
Embedded Flash 0x80000000 256KByte 128KByte 64KByte
EBI SRAM CS0 0xC0000000 16MByte 16MByte 16MByte
EBI SRAM CS2 0xC8000000 16MByte 16MByte 16MByte
EBI SRAM CS3 0xCC000000 16MByte 16MByte 16MByte
EBI SRAM CS4 0xD8000000 16MByte 16MByte 16MByte
EBI SRAM CS5 0xDC000000 16MByte 16MByte 16MByte
EBI SRAM CS1
/SDRAM CS0
0xD0000000 128MByte 128MByte 128MByte
USB Data 0xE0000000 64KByte 64KByte 64KByte