Datasheet

65
32072SH–AVR32–10/2012
AT32UC3A3
Figure 7-12. SPI Master mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
Figure 7-13. SPI Slave mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
Figure 7-14. SPI Slave mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)
SPCK
MISO
MOSI
SPI
5
SPI
3
SPI
4
SPCK
MISO
MOSI
SPI
6
SPI
7
SPI
8
SPCK
MISO
MOSI
SPI
9
SPI
10
SPI
11