User manual

Glossary

Index See Cache index.

Index register A register specified in some load or store instructions. The value of this register is used

as an offset to be added to or subtracted from the base register value to form the virtual

address, which is sent to memory. Some addressing modes optionally enable the index

Instruction cache A block of on-chip fast access memory locations, situated between the processor and

main memory, used for storing and retrieving copies of often used instructions. This is

done to greatly reduce the average speed of memory accesses and so to increase

processor performance.

Instruction cycle count

The number of cycles for which an instruction occupies the Execute stage of the

pipeline.

Instruction Memory Barrier (IMB)

An operation to ensure that the prefetch buffer is flushed of all out-of-date instructions.

Internal scan chain A series of registers connected together to form a path through a device, used during

production testing to import test patterns into internal nodes of the device and export the

resulting values.

Interrupt handler A program that control of the processor is passed to when an interrupt occurs.

Interrupt vector One of a number of fixed addresses in low memory, or in high memory if high vectors

are configured, that contains the first instruction of the corresponding interrupt handler.

Invalidate To mark a cache line as being not valid by clearing the valid bit. This must be done

whenever the line does not contain a valid cache entry. For example, after a cache flush

all lines are invalid.

Joint Test Action Group (JTAG)

The name of the organization that developed standard IEEE 1149.1. This standard

defines a boundary-scan architecture used for in-circuit testing of integrated circuit

devices. It is commonly known by the initials JTAG.

JTAG See Joint Test Action Group.

Line See Cache line.

Little-endian Byte ordering scheme in which bytes of increasing significance in a data word are stored

at increasing addresses in memory.