Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsPMICsPMIC - motor controllers Half-bridge (3) Seriell SO 14

9213D–AUTO–09/12

Features

● Supply voltage up to 40V

● R

DSon

typically 0.8Ω at 25°C, Maximum 1.5Ω at 150°C

● Up to 1.0A output current

● Three half-bridge outputs formed by three high-side and three low-side drivers

● Capable of switching all kinds of loads such as DC motors, bulbs, resistors,

capacitors and inductors

● No shoot-through current

● Very low quiescent current I

< 2µA in Standby Mode versus total temperature

range

● Outputs short-circuit protected

● Overtemperature protection for each switch and overtemperature prewarning

● Undervoltage protection

● Various diagnostic functions such as shorted output, open-load, overtemperature

and power-supply fail detection

● Serial data interface, Daisy Chain capable, up to 2MHz clock frequency

● SO14 power package

Atmel ATA6826C

Triple Half-bridge DMOS Output Driver with Serial Input

Control

DATASHEET

Summary of content (16 pages)

PAGE 1
Atmel ATA6826C Triple Half-bridge DMOS Output Driver with Serial Input Control DATASHEET Features ● Supply voltage up to 40V ● RDSon typically 0.8Ω at 25°C, Maximum 1.5Ω at 150°C ● Up to 1.
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1. Description The Atmel® ATA6826C is a fully protected Triple Half-bridge designed in Smart Power SOI Technology, used to control up to three different loads by a microcontroller in automotive and industrial applications. Each of the three high-side and three low-side drivers is capable of driving currents up to 1.0A. The drivers are internally connected to form three half-bridges and can be controlled separately from a standard serial data interface.
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2. Pin Configuration Figure 2-1. Pinning SO14 GND OUT3 VS CS DI CLK GND Table 2-1.
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3. Functional Description 3.1 Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and is accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS.
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Table 3-2. Output Data Protocol Bit Output (Status) Register 0 TP 1 Status LS1 High = output is on, low = output is off; not affected by SRR 2 Status HS1 High = output is on, low = output is off; not affected by SRR 3 Status LS2 Description see LS1 4 Status HS2 Description see HS1 5 Status LS3 Description see LS1 6 Status HS3 Description see HS1 7 n. u. Not used 8 n. u. Not used 9 n. u. Not used 10 n. u. Not used 11 n. u. Not used 12 n. u.
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3.2 Power-supply Fail In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register is set and all outputs are disabled. To detect an undervoltage, its duration has to be longer than the undervoltage detection delay time tdUV. The outputs are enabled immediately when supply voltage recovers to a normal operating value. The PSF bit stays high until it is reset by the SRR (Status Register Reset) bit in the input register. 3.
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4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All values refer to GND pins.
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7. Noise and Surge Immunity Parameters Test Conditions Conducted interferences ISO 7637-1 Interference suppression VDE 0879 Part 2 Value Level 4(1) Level 5 ESD (Human Body Model); pins 2, 12, 13 vs. GND HBM: AEC-Q100-002-Ref-D CEI/IEC 60749-26:2006 ESD (Human Body Model), all other pins ESDA/JEDEC JS-001-2010 8kV CDM (Charged Device Model) ANSI/ESD S5.3.1-2009 1kV MM (Machine Model) AEC Q100-003-REV-E ANSI/ESD S5.2-2009 250V Note: 8.
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8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.75V < VVCC < 5.25V; INH = High; –40°C < Tj < 150° C; unless otherwise specified, all values refer to GND pins. No. 3 Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* TjPW set 120 145 170 °C B 105 130 155 °C B °C B Thermal Prewarning and Shutdown 3.1 Thermal prewarning set 3.2 Thermal prewarning reset TjPW reset 3.3 Thermal prewarning hysteresis ΔTjPW 3.
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8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.75V < VVCC < 5.25V; INH = High; –40°C < Tj < 150° C; unless otherwise specified, all values refer to GND pins. No. Parameters 4.12 Symbol Min. Max. Unit Type* Open-load detection delay time tdSd 200 600 µs A 4.13 High-side output switch VVS = 13V on delay(1) RLoad = 30Ω tdon 20 µs A 4.14 Low-side output switch VVS = 13V on delay(1) RLoad = 30Ω tdon 20 µs A 4.
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9. Serial Interface – Timing Pin Timing Chart No.(1) Symbol CDO = 100pF 9 1 DO disable after CS rising edge CDO = 100pF 9 8.3 DO fall time CDO = 100pF 8.4 DO rise time 8.5 DO valid time 8.6 8.7 No. Parameters Test Conditions 8.1 DO enable after CS falling edge 8.2 Min. Typ. Max.
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Figure 9-1. Serial Interface Timing with Chart Numbers 1 2 CS DO 9 CS 4 7 CLK 5 3 6 8 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.3 × VCC Output DO: High level = 0.8 × VCC, low level = 0.
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10. Application Circuit Figure 10-1. Application Circuit VCC Enable Trigger Reset Atmel U5021M Watchdog VS n. u. n. u. O C S n. u. n. u. n. u. n. u. n. u. n. u. H S 3 H S 2 L S 3 H S 1 L S 2 L S 1 S R R BYT41D 3 VS VBatt Microcontroller CLK CS 5 P S F O P L S C D n. u. n. u. DO n. u. n. u. n. u. n. u.
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Ordering Information Extended Type Number Package ATA6826C-TUQY Remarks Power package, taped and reeled, lead-free Package Information 1 7 14 technical drawings according to DIN specifications 8 Dimensions in mm C D A b A1 13. SO14 A2 12. e E1 L E COMMON DIMENSIONS Note1): Dimensions “D” and “E1” do not include Moldflash or protrusion. (MAX. 0.15mm per side) Bemerkung: ASE (Unit of Measure = mm) Symbol MIN NOM A 1.35 1.55 MAX 1.75 A1 A2 0.10 1.25 0.18 1.38 0.25 1.50 0.
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14. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 9213D-AUTO-09/12 • Section 7 “Noise and Surge Immunity” on page 8 changed 9213C-AUTO-05/12 • Section 13 “Package Information” on page 14 changed 9213B-BCD-01/11 • Section 3.
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