ATBTLC1000 Hardware Design Guidelines Ultra Low Power BLE 4.1 SoC USER GUIDE VDDIO VBAT Antenna Chip_En AO_GPIO_0 LP_GPIO ATBTLC1000 BLE 4.1 SOC Matching GPIO_MS1/MS2 26MHz From 32.768kHz crystal or clock Block Diagram Introduction This document details the hardware design guidelines for a customer to design the Atmel® ATBTLC1000 IC onto their board.
Ta bl e of Conte nts 1 Reference Schematic................................................................................................... 3 1.1 2 Notes on Interfacing to the ATBTLC1000 ................................................................... 5 2.1 2.2 2.3 2.4 3 Programmable Pull-up Resistors ........................................................................................................... 5 Using an External RTC ...................................................................
1 Reference Schematic 1.1 Schematic Figure 1-1 shows the reference schematic for a system using the ATBTLC1000. Figure 1-1. Reference Schematic ATBTLC1000 Hardware Design Guidelines – Ultra Low Power BLE 4.
Figure 1-2 shows the Bill of Materials for the schematic. Figure 1-2. 4 Bill of Materials ATBTLC1000 Hardware Design Guidelines – Ultra Low Power BLE 4.
2 Notes on Interfacing to the ATBTLC1000 2.1 Programmable Pull-up Resistors The ATBTLC1000 provides programmable pull-up resistors on various pins. The purpose of these resistors is to keep any unused input pins from floating which can cause excess current to flow through the input buffer from the VDDIO supply. Any unused module pin on the ATBTLC1000 should leave these pull-up resistors enabled so the pin will not float. The default state at power up is for the pull-up resistor to be enabled.
Figure 2-1. ATBTLC1000 XO Connections to Low Frequency Crystal Oscillator (a) Crystal Oscillator is used Table 2-1. (b) Crystal Oscillator is bypassed ATBTLC1000 32.768kHz External Clock Specification Parameter Min. Oscillation frequency Typ. Max. 32.768 Unit KHz Comments Must be able to drive 6pF load @ desired frequency VinH 0.7 1.2 V High level input voltage VinL 0 0.
2.3 Restrictions for Power States When VDDIO is off (either disconnected or at ground potential), a voltage must not be applied to the device pins. This is because each pin contains an ESD diode from the pin to the VDDIO supply. This diode will turn on when a voltage higher than one diode-drop is supplied to the pin. This in turn will try to power up the part through the VDDIO supply. If a voltage must be applied to the signal pads while the chip is in a low power state, the VDDIO supply must be on.
3 Placement and Routing Guidelines It is critical to follow the recommendations listed below to achieve the best RF performance: 3.1 The board should have a solid ground plane. The center ground pad of the device must be solidly connected to the ground plane by using a 3 x 3 grid of vias.
Be sure to place the DC blocking capacitor (C4) and matching components (C5, L4, C4) as close to the RFIO pin as possible. Figure 3-1 shows the placement and routing of these components using the design parameters detailed in the first paragraph of this section. Note that they are placed as close as possible to the ATBTLC1000’s pin 2. The components used for this design are 0201. Note that the width of the route matches the width of the component pads.
Figure 3-2. Placement and Routing of PMU Components Figure 3-3. Inner Layer PMU Route ATBTLC1000 Hardware Design Guidelines – Ultra Low Power BLE 4.
Placement of FB1, C12, and C16 should be as close as possible to the VBAT_BUCK pin (pin 15), with the smaller capacitor, C16, placed closest to the pin. Again, the route should be as heavy as possible to provide a low impedance path. The placement and routing of these components is shown in Figure 3-2. Note that the PMU is a switching regulator and produces noise within the 2.4GHz receive band.
5, a gap exists in the ground plane blocking the return current. This discontinuity in the ground will greatly affect the RF performance and must be avoided at all costs. This example also shows the correct placement of ground vias in the center paddle. Note that there is a ground via placed directly next to the RFIO pin. Figure 3-5. 3.5 Example of an Incorrect Ground Plane VDDIO VDDIO (pin 26) is also a supply input pin and the route to this should be a large power route.
3.7 Sensitive Routes The following signals are very sensitive to noise and one must take care to keep them as short as possible and keep them isolated from all other signals by routing them far away from other traces or by using ground to shield them. Pay special attention to routes on layers above and below these routes. Any noisy signals running above or below these signals on other layers will couple noise into these routes: XO_N XO_P RFIO 3.
Figure 3-7. Routing of 1P2V Supply Additionally, while the VBAT_BUCK (pin 15) supply is not sensitive to picking up noise, it is a noise generating supply. Therefore, be sure to keep the decoupling capacitors for this supply pin as close as possible to the VBAT_BUCK pin and make sure that the route for this supply stays far away from sensitive pins and supplies. 3.9 Additional Suggestions Make sure that traces route directly through the pads of all filter capacitors and not by a stub route.
Figure 3-9. 4 Incorrect Stub Route To Capacitor Pad Interferers One of the major problems with RF receivers is poor performance due to interferers on the board radiating noise into the antenna or coupling into the RF traces going to input LNA. Care must be taken to make sure that there is no noisy circuitry placed anywhere near the antenna or the RF traces. All noise generating circuits should also be shielded so they do not radiate noise that is picked up by the antenna.
6 Reference Documentation and Support 6.1 Reference Documents Atmel offers a set of collateral documentation to ease integration and device ramp. Table 6-1 shows a list of documents available on the Atmel web or integrated into development tools. Table 6-1. Document List Title Content ATBTLC1000 QFN SoC, Datasheet Design Files Package User Guide, Schematic, PCB layout, Gerber, BOM & System notes on: RF/Radio Full Test Report, radiation pattern, design guidelines, temperature performance, ESD.
7 ATMEL EVALUATION BOARD/KIT IMPORTANT NOTICE AND DISCLAIMER This evaluation board/kit is intended for user's internal development and evaluation purposes only. It is not a finished product and may not comply with technical or legal requirements that are applicable to finished products, including, without limitation, directives or regulations relating to electromagnetic compatibility, recycling (WEEE), FCC, CE or UL.
8 Revision History Doc Rev. 42537B 42537A 18 Date 10/2015 09/2015 Comments The document title is updated Figure 1-1 and Figure 1-2 are updated New Section 2.2 is added Section 3.2 is updated Section 3.3 is updated Figure 3-2 is updated New Section 3.4 is added Initial document release. ATBTLC1000 Hardware Design Guidelines – Ultra Low Power BLE 4.
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