Datasheet

ATBTLC1000 Hardware Design Guidelines – Ultra Low Power BLE 4.1 SoC [USER GUIDE]
Atmel-42537B-ATBTLC1000-Hardware-Design-Guidelines_UserGuide_102015
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5, a gap exists in the ground plane blocking the return current. This discontinuity in the ground will greatly
affect the RF performance and must be avoided at all costs. This example also shows the correct
placement of ground vias in the center paddle. Note that there is a ground via placed directly next to the
RFIO pin.
Figure 3-5. Example of an Incorrect Ground Plane
3.5 VDDIO
VDDIO (pin 26) is also a supply input pin and the route to this should be a large power route. The
decoupling capacitor for this supply (C11) should be placed as close as possible to the pin. Figure 3-6
shows the placement of the decoupling capacitor and the route to this power pin.
Figure 3-6. VDDIO Route and Decoupling Capacitor Placement
3.6 LP_LDO_OUT
LP_LDO_OUT (pin20) is the output of an on-chip regulator. It requires a 1µF ceramic capacitor (C13) to
be placed as close as possible to the pin.