Datasheet

ATBTLC1000 Hardware Design Guidelines – Ultra Low Power BLE 4.1 SoC [USER GUIDE]

Atmel-42537B-ATBTLC1000-Hardware-Design-Guidelines_UserGuide_102015

3.7 Sensitive Routes

The following signals are very sensitive to noise and one must take care to keep them as short as

possible and keep them isolated from all other signals by routing them far away from other traces or by

using ground to shield them. Pay special attention to routes on layers above and below these routes. Any

noisy signals running above or below these signals on other layers will couple noise into these routes:

XO_N

XO_P

RFIO

3.8 Supply Pins

The following are power supply pins for the ATBTLC1000. They are supplied with approximately 1.2V by

the on-chip PMU. It is important that the decoupling capacitors for these supplies are placed as close to

the ATBTLC1000 pin as possible. This is necessary to reduce the trace inductance between the capacitor

and ATBTLC1000 power pin to an absolute minimum:

VDDRF (pin 1)

VDD_AMS (pin 3)

VDD_SXDIG (pin 31)

VDD_VCO (pin 32)

VDDC_PD4 (pin16)

Place one 0.1µF capacitor as close as possible to pins 3, 31 and 32. Place a 1µF capacitor as close as

possible to pin 3.

The route going from C14 in the reference schematic to pins 1, 3, 16, 31, and 32 is a power route. It

should be as short and heavy as possible. Try to route it as a power plane on an inner layer. In Figure 3-7,

shown in grey, is an example of a route of this supply on an inner layer of a PCB. The three vias in the

upper left portion go to C14 and the 1.2V route on the top layer, visible in Figure 3-2. The via below and to

the right goes to ATBTLC1000 pin 16 and vias in the bottom right go to pins 1, 3, 31, and 32.