Datasheet

ATBTLC1000 Hardware Design Guidelines – Ultra Low Power BLE 4.1 SoC [USER GUIDE]

Atmel-42537B-ATBTLC1000-Hardware-Design-Guidelines_UserGuide_102015

2 Notes on Interfacing to the ATBTLC1000

2.1 Programmable Pull-up Resistors

The ATBTLC1000 provides programmable pull-up resistors on various pins. The purpose of these

resistors is to keep any unused input pins from floating which can cause excess current to flow through

the input buffer from the VDDIO supply. Any unused module pin on the ATBTLC1000 should leave these

pull-up resistors enabled so the pin will not float. The default state at power up is for the pull-up resistor to

be enabled. However, any pin which is used should have the pull-up resistor disabled. The reason for this

is that if any pins are driven to a low level while the ATBTLC1000 is in the low power sleep state, current

will flow from the VDDIO supply through the pull-up resistors, increasing the current consumption of the

device. Since the value of the pull-up resistor is approximately 100kΩ, the current through any pull-up

resistor that is being driven low will be VDDIO/100K. For VDDIO = 3.3V, the current through each pull-up

resistor that is driven low would be approximately 3.3V/100kΩ = 33µA. Pins which are used and have had

the programmable pull-up resistor disabled, should always be actively driven to either a high or low level

and not be allowed to float.

See the ATBTLC1000 Programming Guide for information on enabling/disabling the programmable pull

up resistors.

2.2 Using an External RTC

The ATBTLC1000 requires a 32.768kHz clock. This can be supplied by connecting a 32.768kHz crystal to

the RTC_CLKP and RTC_CLKN pins as shown in the reference schematic. Alternatively, if a 32.768kHz

clock is already available in the system (from a host MCU, for example), this clock can be used thereby

saving the cost of the crystal. To use the external clock, connect it to the RTC_CLKP pin of the ATBTLC1000

device.

The block diagram in Figure 2-1(a) shows how the internal low frequency Crystal Oscillator (XO) is

connected to the external crystal.

Typically, the crystal should be chosen to have a load capacitance of 7pF to minimize the oscillator

current. The ATBTLC1000 device has switchable on chip capacitance that can be used to adjust the total

load the crystal sees to meet its load capacitance specification. Refer to the ATBTLC1000 QFN SoC

datasheet for more information.

Alternatively, if an external 32.768kHz clock is available, it can be used to drive the RTC_CLKP pin

instead of using a crystal. The XO has 5.625F internal capacitance on the RTC_CLKP pin. To bypass the

crystal oscillator an external signal capable of driving 5.625pF can be applied to the RTC_CLK_P terminal

as shown in Figure 2-1(b). This signal must be 1.2V maximum. RTC_CLK_N must be left unconnected

when driving an external source into RTC_CLK_P.