Datasheet

ATBTLC1000 Hardware Design Guidelines – Ultra Low Power BLE 4.1 SoC [USER GUIDE]
Atmel-42537B-ATBTLC1000-Hardware-Design-Guidelines_UserGuide_102015
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2.3 Restrictions for Power States
When VDDIO is off (either disconnected or at ground potential), a voltage must not be applied to the
device pins. This is because each pin contains an ESD diode from the pin to the VDDIO supply. This
diode will turn on when a voltage higher than one diode-drop is supplied to the pin. This in turn will try to
power up the part through the VDDIO supply.
If a voltage must be applied to the signal pads while the chip is in a low power state, the VDDIO supply
must be on.
Similarly, to prevent the pin-to-ground diode from turning on, do not apply a voltage that is more than one
diode-drop below ground to any pin.
2.4 Power-up Sequence
The power-up sequence for ATBTLC1000 is shown in Figure 2-3. The timing parameters are provided in
Table 2-2.
Figure 2-3. Power-up Sequence
VBATT
VDDIO
CHIP_EN
t
BIO
t
IOCE
Table 2-2. Power-up Sequence Timing
Parameter
Min.
Max.
Unit
Description
Notes
t
BIO
0
ms
VBATT rise to VDDIO
rise
VBATT and VDDIO can rise simultaneously or
can be tied together
t
IOCE
0
ms
VDDIO rise to CHIP_EN
rise
CHIP_EN must not rise before VDDIO.
CHIP_EN must be driven high or low, not left
floating