Datasheet

ATBTLC1000 Hardware Design Guidelines – Ultra Low Power BLE 4.1 SoC [USER GUIDE]

Atmel-42537B-ATBTLC1000-Hardware-Design-Guidelines_UserGuide_102015

3 Placement and Routing Guidelines

It is critical to follow the recommendations listed below to achieve the best RF performance:

 The board should have a solid ground plane. The center ground pad of the device must be solidly

connected to the ground plane by using a 3 x 3 grid of vias.

 Keep away from antenna, as far as possible, and large metal objects, to avoid electromagnetic field

blocking

 Do not enclose the antenna within a metal shield

 Keep any components which may radiate noise or signals within the 2.4 – 2.5GHz frequency band

far away from the antenna, or better yet, shield those components. Any noise radiated from the

main board in this frequency band will degrade the sensitivity of the module.

3.1 Power and Ground

Dedicate one layer as a ground plane. Make sure that this ground plane does not get broken up by routes.

Power can route on all layers except the ground layer. Power supply routes should be heavy copper fill

planes to insure the lowest possible inductance. The power pins of the NMC1000 should have a via

directly to the power plane as close to the pin as possible. Decoupling capacitors should have a via right

next to the capacitor pin and this via should go directly down to the power plane – that is to say, the

capacitor should not route to the power plane through a long trace. The ground side of the decoupling

capacitor should have a via right next to the pad which goes directly down to the ground plane. Each

decoupling capacitor should have its own via directly to the ground plane and directly to the power plane

right next to the pad. The decoupling capacitors should be placed as close to the pin that it is filtering as

possible.

3.2 RF Traces and Components

The RF trace that routes from the ATBTLC1000’s RFIO pin to the antenna must be 50Ω controlled

impedance. This is pin 2 of the 32-pin QFN package. This controlled impedance trace must reference a

ground plane on a lower layer. To achieve 50Ω impedance, a typical design might implement a coplanar

waveguide utilizing 1oz copper and a dielectric constant of 4.0 with a 12 mil wide trace and 6 mil spacing

on either side to the top layer ground and referenced to a ground plane on an inner layer, which is 6.5 mils

below the trace. This must be adjusted depending on the dielectric and copper weight used. No other

traces must route through the RF area on layers between the RF traces and the ground reference plane.

In fact, try not to route any other traces in the RF area on any layer. This ground reference plane must

extend entirely under the ATBTLC1000 package.

Be sure that the route from pin 2 to the antenna is as short as possible to reduce path losses and to

minimize the opportunity for the trace to pick up noise.

Be sure to add as many ground vias as possible, tying all ground layers together (ground stitching) all

along the RF traces and throughout the area where the RF traces are routed. Add at least one ground via

right next to the ground pad of each of the components in the RF path. Place ground vias all along the RF

traces on either side.

Tie the center ground pad of the ATBTLC1000 to the inner ground layer using a grid of nine vias. The

ground path going from the ground pad down to the ground plane must have as low impedance as

absolutely possible. The ground return path for the RF must not be broken. It must be a solid, continuous,

unbroken low impedance path.

Do not use thermal relief pads for the ground pads of all components in the RF path. These component

pads must be completely filled in with ground copper.