Datasheet

ATBTLC1000 Hardware Design Guidelines – Ultra Low Power BLE 4.1 SoC [USER GUIDE]

Atmel-42537B-ATBTLC1000-Hardware-Design-Guidelines_UserGuide_102015

Be sure to place the DC blocking capacitor (C4) and matching components (C5, L4, C4) as close to the

RFIO pin as possible. Figure 3-1 shows the placement and routing of these components using the design

parameters detailed in the first paragraph of this section. Note that they are placed as close as possible to

the ATBTLC1000’s pin 2. The components used for this design are 0201. Note that the width of the route

matches the width of the component pads. This will avoid impedance discontinuities which would occur if

there is a large mismatch in trace width versus the component pad size.

Figure 3-1. Placement and Routing of DC Blocking Cap and Matching Components

Be sure that the route from the antenna to the ATBTLC1000 is as short as possible and is completely

isolated from all other signals on the board. No signals should route under this trace on any layer of the

board. Make sure that all digital signals that may be toggling while the ATBTLC1000 is active are placed

as far away from the antenna as possible. No connectors which have digital signals going to them should

be near the antenna. All digital components and switching regulators on the board should be shielded so

they do not radiate any noise that can be picked up by the antenna.

In summary, make sure that anything that switches is shielded and kept away from the antenna, the

ATBTLC1000, or the route from the ATBTLC1000 to the antenna.

3.3 Power Management Unit (PMU)

The ATBTLC1000 contains an on-chip switching regulator, which regulates the VBAT supply down to

approximately 1.2V for supplying the rest of the device. It is crucial to place and route the components

associated with this circuit correctly to ensure proper operation and especially to reduce any radiated

noise, which can be picked up by the antenna and can severely reduce the receiver sensitivity. The

external components for the PMU consist of two inductors, L5 = 15nH and L6 = 4.7µH and a capacitor,

C14 = 4.7µF. These components must be placed as close as possible to ATBTLC1000 pin 14. The

smaller inductor, L5, must be placed closest to pin 14. Current will flow from pin 14, through L5, then L6,

and then through C14 to ground and back to the center ground paddle of the ATBTLC1000 package.

Place components so this current loop is as small as possible. Make sure there is a ground via to the

inner ground plane right next to the ground pin of C14. The ground return path must be extremely low

inductance. Failure to provide a short, heavy ground return between the capacitor and the ATBTLC1000

ground pad will result in incorrect operation of the on chip switching regulator. Figure 3-2 shows an

example placement and routing of these components. The current loop described above is indicated by

the red line, with the dashed portions indicating the path on inner layers. The route from pin 14 to L5 is on

an inner layer and is shown in Figure 3-3 in red/white.