User Manual

CONFIDENTIAL
© 2000~2011 iSSC Technologies Corp.
9
Timing Sequence for Rest Pin (RST_N) under different mode
22 I
RST_N External reset input (Low Active), clock period 62.5n at least.
External Rest
Write Flash Mode
Test Mode
1 ms
APP Mode
RST_N Timing Diagram
60 ms
5 ms
400 ms
2
1
3
Ready
for MCU
Ready
for MCU
Ready
for MCU