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 2011 Microchip Technology Inc. DS80495E-page 1

PIC18F87J11 FAMILY

The PIC18F87J11 family devices that you have

received conform functionally to the current Device

Data Sheet (DS39778D), except for the anomalies

described in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be

addressed in future revisions of the PIC18F87J11

family silicon.

Data Sheet clarifications and corrections start on page 5,

following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2 or

PICkit™ 3:

1. Using the appropriate interface, connect the

device to the MPLAB ICD 2 programmer/

debugger or PICkit™ 3.

2. From the main menu in MPLAB IDE, select

Configure>Select Device

, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger>Select Tool

4. Perform a “Connect” operation to the device

(Debugger>Connect

). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window.

The DEVREV values for the various PIC18F87J11

family silicon revisions are shown in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A6) or (C2), respectively.

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

Revision ID for Silicon Revision

(2)

A1 A2 A4 A5 A6 C1 C2

PIC18F66J11 444h

1h 2h 4h 5h 6h

10h 13hPIC18F66J16 446h

PIC18F67J11 448h

PIC18F86J11 44Eh

PIC18F86J16 450h

PIC18F87J11 452h

Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration

memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.

2: Refer to the “PIC18F6XJXX/8XJXX Flash Microcontroller Programming Specification” (DS39644) for

detailed information on Device and Revision IDs for your specific device.

PIC18F87J11 Family

Silicon Errata and Data Sheet Clarification

Summary of content (18 pages)

PAGE 1
PIC18F87J11 FAMILY PIC18F87J11 Family Silicon Errata and Data Sheet Clarification The PIC18F87J11 family devices that you have received conform functionally to the current Device Data Sheet (DS39778D), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2 or PICkit™ 3: 1. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1.
PAGE 2
PIC18F87J11 FAMILY TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Num Affected Revisions(1) Issue Summary A1 A2 A4 A5 A6 C1 C2 1. When configured for I C slave reception, the MSSPx module may not receive the correct data if the SSPxBUF register is not read within a window after an SSPxIF interrupt occurs. X X X X X X X 2. When Phase Lock Loop (PLL) is enabled, if the PLL input frequency is higher than 8 MHz, there may be problems accessing the RAM. X X 3.
PAGE 3
PIC18F87J11 FAMILY 3. Module: Voltage Regulator Silicon Errata Issues This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A6) or (C2), respectively. If VDDCORE drops below approximately 2.
PAGE 4
PIC18F87J11 FAMILY 4. Module: SRAM 5. Module: Low-Voltage Detect Any access to SRAM, either in the form of read or write operations, will increase the current consumption of the device, depending on how often the SRAM is accessed. A small current increase is normal, but in this cited silicon revision, the difference may be significant and of particular concern for low-power applications. The LVDSTAT, VDDCORE status bit (WDTCON<6>), is not implemented in this revision of silicon. Work around None.
PAGE 5
PIC18F87J11 FAMILY Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39778D): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: Table 27-1: Memory Programming Requirements On page 398, the parameter, D132, which provides the minimum and maximum voltage levels of the Self-Timed Erase or Write for VDD and VDDCORE, are included.
PAGE 6
PIC18F87J11 FAMILY 2. Module: Table 27-2: Comparator Specifications On page 399, the maximum Input Offset Voltage (Parameter No. D300) is changed to ±25 mV. The parameter numbers for TRESP and TMC2OV are changed to D303 and D304, respectively. A new parameter, D305, for VIRV is added. The changed/appended values are indicated in bold text in the following table: TABLE 27-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param No.
PAGE 7
PIC18F87J11 FAMILY 4. Module: Section 27.3 “DC Characteristics: PIC18F87J11 Family (Industrial)” On page 396, the characteristics and conditions of the Input Leakage Current are updated for the Analog (D060) and included for the Digital (D060A) I/O ports. The changed values are indicated in bold text in the following table: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA  +85°C for industrial DC CHARACTERISTICS Param Symbol No.
PAGE 8
PIC18F87J11 FAMILY 5. Module: Example 6-2: Erasing a Flash Program Memory Row On page 94, an instruction to enable the write process to memory for erasing the Flash programming memory row is missing in the example.
PAGE 9
 2011 Microchip Technology Inc.
PAGE 10
PIC18F87J11 FAMILY 8. Module: Figure 19-24: I2C™ Master Mode Waveform (Reception, 7-Bit Address) On page 261, the condition (R/W) when the Acknowledge signal (ACK) is received from the slave, after transmitting the address to the slave, is changed to ‘1’. The changed value is indicated in bold text in Figure 19-24. DS80495E-page 10  2011 Microchip Technology Inc.
PAGE 11
 2011 Microchip Technology Inc.
PAGE 12
PIC18F87J11 FAMILY 9. Module: Table 1-3: PIC18F6XJ1X Pinout I/O Descriptions On page 20, the pin type for the RF3, RF4 and RF5 pins is changed from I (Input) to I/O (Input/Output). The changed content is indicated in bold text in the following table. Pin Number Pin Name 64-TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port.
PAGE 13
PIC18F87J11 FAMILY 10. Module: Memory Organization On page 75, the note at the end of Section 5.3.4 “Special Function Registers” has been amended. The new information is indicated in bold text. Note: 11. Module: Memory Organization On page 73, in Figure 5-7, Note 2 has been added. The additional note is indicated in bold text in Figure 5-7. Addresses, F5Ah through F5Fh, are not part of the Access Bank. These registers must always be accessed using the Bank Select Register.
PAGE 14
PIC18F87J11 FAMILY FIGURE 5-7: DATA MEMORY MAP FOR PIC18F87J11 FAMILY DEVICES When a = 0: BSR<3:0> Data Memory Map 00h = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 Access RAM Bank 0 FFh 00h Bank 1 Bank 2 1FFh 200h GPR FFh 00h Bank 3 2FFh 300h The first 96 bytes are general purpose RAM (from Bank 0). The remaining 160 bytes are Special Function Registers (from Bank 15).
PAGE 15
PIC18F87J11 FAMILY 12. Module: Electrical Specification Changes have been made to the VBOR specification, Parameter Number D005 in Table 27.1, as shown in bold text in the updated table below. 27.1 DC Characteristics: Supply Voltage PIC18F87J11 Family (Industrial) PIC18F87J11 Family (Industrial) Param No.
PAGE 16
PIC18F87J11 FAMILY DOCUMENT REVISION HISTORY Rev A Document (2/2010) Combined existing silicon and data sheet errata documents into the new, single document format. Added the A6 silicon revision, but no issues or clarifications. This document replaces these errata documents: • DS80418A, “PIC18F87J11 Family Rev. A5 Silicon Errata” • DS80417A, “PIC18F87J11 Family Rev. A4 Silicon Errata” • DS80344A, “PIC18F87J11 Family Rev. A2 Silicon Errata” • DS80305B, “PIC18F87J11 Family Rev.
PAGE 17
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 18
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