Datasheet

ENC28J60
DS39662E-page 34 .  2006-2012 Microchip Technology Inc.
6.5 MAC Initialization Settings
Several of the MAC registers require configuration
during initialization. This only needs to be done once;
the order of programming is unimportant.
1. Set the MARXEN bit in MACON1 to enable the
MAC to receive frames. If using full duplex, most
applications should also set TXPAUS and
RXPAUS to allow IEEE defined flow control to
function.
2. Configure the PADCFG, TXCRCEN and
FULDPX bits of MACON3. Most applications
should enable automatic padding to at least
60 bytes and always append a valid CRC. For
convenience, many applications may wish to set
the FRMLNEN bit as well to enable frame length
status reporting. The FULDPX bit should be set
if the application will be connected to a
full-duplex configured remote node; otherwise, it
should be left clear.
3. Configure the bits in MACON4. For confor-
mance to the IEEE 802.3 standard, set the
DEFER bit.
4. Program the MAMXFL registers with the maxi-
mum frame length to be permitted to be received
or transmitted. Normal network nodes are
designed to handle packets that are 1518 bytes
or less.
5. Configure the Back-to-Back Inter-Packet Gap
register, MABBIPG. Most applications will pro-
gram this register with 15h when Full-Duplex
mode is used and 12h when Half-Duplex mode
is used.
6. Configure the Non-Back-to-Back Inter-Packet
Gap register low byte, MAIPGL. Most applications
will program this register with 12h.
7. If half duplex is used, the Non-Back-to-Back
Inter-Packet Gap register high byte, MAIPGH,
should be programmed. Most applications will
program this register to 0Ch.
8. If Half-Duplex mode is used, program the
Retransmission and Collision Window registers,
MACLCON1 and MACLCON2. Most applications
will not need to change the default Reset values.
If the network is spread over exceptionally long
cables, the default value of MACLCON2 may
need to be increased.
9. Program the local MAC address into the
MAADR1:MAADR6 registers.
REGISTER 6-1: MACON1: MAC CONTROL REGISTER 1
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — r TXPAUS RXPAUS PASSALL MARXEN
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 Reserved: Maintain as ‘0’
bit 3 TXPAUS: Pause Control Frame Transmission Enable bit
1 = Allow the MAC to transmit pause control frames (needed for flow control in full duplex)
0 = Disallow pause frame transmissions
bit 2 RXPAUS: Pause Control Frame Reception Enable bit
1 = Inhibit transmissions when pause control frames are received (normal operation)
0 = Ignore pause control frames which are received
bit 1 PASSALL: Pass All Received Frames Enable bit
1 = Control frames received by the MAC will be written into the receive buffer if not filtered out
0 = Control frames will be discarded after being processed by the MAC (normal operation)
bit 0 MARXEN: MAC Receive Enable bit
1 = Enable packets to be received by the MAC
0 = Disable packet reception