Datasheet

ENC28J60
DS39662E-page 40 .  2006-2012 Microchip Technology Inc.
FIGURE 7-2: SAMPLE TRANSMIT PACKET LAYOUT
To achieve the example layout shown in Figure 7-2 and
to transmit a packet, the host controller should:
1. Appropriately program the ETXST Pointer to
point to an unused location in memory. It will
point to the per packet control byte. In the
example, it would be programmed to 0120h. It is
recommended that an even address be used for
ETXST.
2. Use the WBM SPI command to write the per
packet control byte, the destination address, the
source MAC address, the type/length and the
data payload.
3. Appropriately program the ETXND Pointer. It
should point to the last byte in the data payload.
In the example, it would be programmed to
0156h.
4. Clear EIR.TXIF, set EIE.TXIE and set EIE.INTIE
to enable an interrupt when done (if desired).
5. Start the transmission process by setting
ECON1.TXRTS.
If a DMA operation was in progress while the TXRTS bit
was set, the ENC28J60 will wait until the DMA opera-
tion is complete before attempting to transmit the
packet. This possible delay is required because the
DMA and transmission engine share the same memory
access port. Similarly, if the DMAST bit in ECON1 is set
after TXRTS is already set, the DMA will wait until the
TXRTS bit becomes clear before doing anything. While
the transmission is in progress, none of the unshaded
bits (except for the ECON1 register’s bits) in Table 7-2
should be changed. Additionally, none of the bytes to be
transmitted should be read or written to through the SPI.
If the host controller wishes to cancel the transmission,
it can clear the TXRTS bit.
When the packet is finished transmitting or is aborted
due to an error/cancellation, the ECON1.TXRTS bit will
be cleared, a seven-byte transmit status vector will be
written to the location pointed to by ETXND + 1, the
EIR.TXIF will be set and an interrupt will be generated
(if enabled). The ETXST and ETXND Pointers will not
be modified. To check if the packet was successfully
transmitted, the ESTAT.TXABRT bit should be read. If
it was set, the host controller may interrogate the
ESTAT.LATECOL bit in addition to the various fields in
the transmit status vector to determine the cause. The
transmit status vector is organized as shown in
Table 7-1. Multi-byte fields are written in little-endian
format.
Control
tsv[7:0]
tsv[15:8]
Address Memory Description
0120h
0121h
0122h
015Ah
015Bh
015Ch
015Dh
0Eh
PHUGEEN, PPADN,
Destination Address,
015Eh
Start of the Next Packet
tsv[23:16]
tsv[31:24]
data[1]
data[2]
tsv[39:32]
tsv[47:40]
tsv[55:48]
0159h
0157h
0158h
0156h
data[m]
Data Packet
Status Vector
Status Vector
ETXST = 0120h
ETXND = 0156h
Type/Length and Data
PCRCEN and POVERRIDE
Written by the Hardware
Source Address,
Buffer Pointers