Datasheet

ENC28J60

DS39662E-page 42 .  2006-2012 Microchip Technology Inc.

TABLE 7-2: SUMMARY OF REGISTERS USED FOR PACKET TRANSMISSION

Name

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on page

EIE INTIE

PKTIE DMAIE LINKIE TXIE rTXERIERXERIE 13

EIR

— PKTIF DMAIF LINKIF TXIF r TXERIF RXERIF 13

ESTAT INT BUFER

rLATECOL— RXBUSY TXABRT CLKRDY

(1)

ECON1 TXRST

RXRST DMAST CSUMEN TXRTS RXEN BSEL1 BSEL0 13

ETXSTL TX Start Low Byte (ETXST<7:0>) 13

ETXSTH

— — — TX Start High Byte (ETXST<12:8>) 13

ETXNDL TX End Low Byte (ETXND<7:0>) 13

ETXNDH

— — — TX End High Byte (ETXND<12:8>) 13

MACON1

— — — r TXPAUS RXPAUS PASSALL MARXEN 14

MACON3 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX 14

MACON4

— DEFER BPEN NOBKOFF — — r r 14

MABBIPG

— Back-to-Back Inter-Packet Gap (BBIPG<6:0>) 14

MAIPGL

— Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>) 14

MAIPGH

— Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>) 14

MACLCON1

— — — — Retransmission Maximum (RETMAX<3:0>) 14

MACLCON2

— — Collision Window (COLWIN<5:0>) 14

MAMXFLL Maximum Frame Length Low Byte (MAMXFL<7:0>) 14

MAMXFLH Maximum Frame Length High Byte (MAMXFL<15:8>) 14

Legend: — = unimplemented, r = reserved bit. Shaded cells are not used.

Note 1: CLKRDY resets to ‘0’ on a Power-on Reset but is unaffected on all other Resets.