Datasheet

 2006-2012 Microchip Technology Inc. . DS39662E-page 43
ENC28J60
7.2 Receiving Packets
7.2.1 ENABLING RECEPTION
Assuming that the receive buffer has been initialized,
the MAC has been properly configured and the receive
filters have been configured to receive Ethernet
packets, the host controller should:
1. If an interrupt is desired whenever a packet is
received, set EIE.PKTIE and EIE.INTIE.
2. If an interrupt is desired whenever a packet is
dropped due to insufficient buffer space, clear
EIR.RXERIF and set both EIE.RXERIE and
EIE.INTIE
3. Enable reception by setting ECON1.RXEN.
After setting RXEN, the Duplex mode and the Receive
Buffer Start and End Pointers should not be modified.
Additionally, to prevent unexpected packets from arriv-
ing, it is recommended that RXEN be cleared before
altering the receive filter configuration (ERXFCON) and
MAC address.
After reception is enabled, packets which are not
filtered out will be written into the circular receive buffer.
Any packet which does not meet the necessary filter
criteria will be discarded and the host controller will not
have any means of identifying that a packet was thrown
away. When a packet is accepted and completely
written into the buffer, the EPKTCNT register will incre-
ment, the EIR.PKTIF bit will be set, an interrupt will be
generated (if enabled) and the Hardware Write Pointer,
ERXWRPT, will automatically advance.
7.2.2 RECEIVE PACKET LAYOUT
Figure 7-3 shows the layout of a received packet. The
packets are preceded by a six-byte header which
contains a Next Packet Pointer, in addition to a receive
status vector which contains receive statistics, includ-
ing the packet’s size. This receive status vector is
shown in Tab le 7- 3.
If the last byte in the packet ends on an odd value
address, the hardware will automatically add a padding
byte when advancing the Hardware Write Pointer. As
such, all packets will start on an even boundary.
FIGURE 7-3: SAMPLE RECEIVE PACKET LAYOUT
Low Byte
High Byte
rsv[7:0]
rsv[15:8]
data[m-3]
data[m-2]
data[m-1]
data[m]
Address Memory Description
1020h
1021h
1022h
1023h
105Ah
105Bh
105Ch
1059h
10h
6Eh
Next Packet Pointer
Packet Data: Destination Address,
Receive Status Vector
crc[31:24]
crc[23:16]
crc[15:8]
crc[7:0]
105Eh
Start of the Next Packet
rsv[23:16]
rsv[30:24]
1024h
1025h
data[1]
1026h
data[2]
1027h
status[7:0]
status[15:8]
status[23:16]
status[31:24]
105Dh
Byte Skipped to Ensure
Even Buffer Address
101Fh
End of the Previous PacketPacket N – 1
Source Address, Type/Length, Data,
Padding, CRC
Packet N
Packet N + 1