Datasheet

 2006-2012 Microchip Technology Inc. . DS39662E-page 61
ENC28J60
11.5 PHY Subsystem Reset
The PHY module may be reset by writing a ‘1’ to the
PRST bit in the PHCON1 register (Register 11-1). All
the PHY register contents will revert to their Reset
defaults.
Unlike other Resets, the PHY cannot be removed from
Reset immediately after setting PRST. The PHY
requires a delay, after which the hardware automati-
cally clears the PRST bit. After a Reset is issued, the
host controller should poll PRST and wait for it to
become clear before using the PHY.
REGISTER 11-1: PHCON1: PHY CONTROL REGISTER 1
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0
PRST PLOOPBK
— — PPWRSV r — PDPXMD
(1)
bit 15 bit 8
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
r — — — — — — —
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PRST: PHY Software Reset bit
1 = PHY is processing a Software Reset (automatically resets to ‘0’ when done)
0 = Normal operation
bit 14 PLOOPBK: PHY Loopback bit
1 = All data transmitted will be returned to the MAC. The twisted-pair interface will be disabled.
0 = Normal operation
bit 13-12 Unimplemented: Read as ‘0’
bit 11 PPWRSV: PHY Power-Down bit
1 = PHY is shut down
0 = Normal operation
bit 10 Reserved: Maintain as ‘0’
bit 9 Unimplemented: Read as ‘0’
bit 8 PDPXMD: PHY Duplex Mode bit
(1)
1 = PHY operates in Full-Duplex mode
0 = PHY operates in Half-Duplex mode
bit 7 Reserved: Maintain as ‘0’
bit 6-0 Unimplemented: Read as ‘0’
Note 1: Reset values of the Duplex mode/status bits depend on the connection of the LED to the LEDB pin (see
Section 2.6 “LED Configuration” for additional details).