Datasheet

ENC28J60
DS39662E-page 66 . 2006-2012 Microchip Technology Inc.
REGISTER 12-3: EIR: ETHERNET INTERRUPT REQUEST (FLAG) REGISTER
U-0 R-0 R/C-0 R-0 R/C-0 R-0 R/C-0 R/C-0
PKTIF DMAIF LINKIF TXIF r TXERIF RXERIF
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as0
bit 6 PKTIF: Receive Packet Pending Interrupt Flag bit
1 = Receive buffer contains one or more unprocessed packets; cleared when PKTDEC is set
0 = Receive buffer is empty
bit 5 DMAIF: DMA Interrupt Flag bit
1 = DMA copy or checksum calculation has completed
0 = No DMA interrupt is pending
bit 4 LINKIF: Link Change Interrupt Flag bit
1 = PHY reports that the link status has changed; read PHIR register to clear
0 = Link status has not changed
bit 3 TXIF: Transmit Interrupt Flag bit
1 = Transmit request has ended
0 = No transmit interrupt is pending
bit 2 Reserved: Maintain as ‘0
bit 1 TXERIF: Transmit Error Interrupt Flag bit
1 = A transmit error has occurred
0 = No transmit error has occurred
bit 0 RXERIF: Receive Error Interrupt Flag bit
1 = A packet was aborted because there is insufficient buffer space or the packet count is 255
0 = No receive error interrupt is pending