Datasheet

 2006-2012 Microchip Technology Inc. . DS39662E-page 73
ENC28J60
14.0 POWER-DOWN
The ENC28J60 may be commanded to power-down
via the SPI interface. When powered down, it will no
longer be able to transmit and receive any packets.
To maximize power savings:
1. Turn off packet reception by clearing
ECON1.RXEN.
2. Wait for any in-progress packets to finish being
received by polling ESTAT.RXBUSY. This bit
should be clear before proceeding.
3. Wait for any current transmissions to end by
confirming ECON1.TXRTS is clear.
4. Set ECON2.VRPS (if not already set).
5. Enter Sleep by setting ECON2.PWRSV. All
MAC, MII and PHY registers become
inaccessible as a result. Setting PWRSV also
clears ESTAT.CLKRDY automatically.
In Sleep mode, all registers and buffer memory will
maintain their states. The ETH registers and buffer
memory will still be accessible by the host controller.
Additionally, the clock driver will continue to operate.
The CLKOUT function will be unaffected (see
Section 2.3 “CLKOUT Pin”).
When normal operation is desired, the host controller
must perform a slightly modified procedure:
1. Wake-up by clearing ECON2.PWRSV.
2. Wait at least 300 s for the PHY to stabilize. To
accomplish the delay, the host controller may
poll ESTAT.CLKRDY and wait for it to become
set.
3. Restore receive capability by setting
ECON1.RXEN.
After leaving Sleep mode, there is a delay of many
milliseconds before a new link is established (assuming
an appropriate link partner is present). The host
controller may wish to wait until the link is established
before attempting to transmit any packets. The link
status can be determined by polling the
PHSTAT2.LSTAT bit. Alternatively, the link change
interrupt may be used if it is enabled. See
Section 12.1.5 “Link Change Interrupt Flag
(LINKIF)” for additional details.
TABLE 14-1: SUMMARY OF REGISTERS USED WITH POWER-DOWN
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
ESTAT INT BUFER r LATECOL — RXBUSY TXABRT CLKRDY
(1)
13
ECON2
AUTOINC PKTDEC PWRSV rVRPS— — — 13
ECON1 TXRST RXRST DMAST CSUMEN TXRTS RXEN BSEL1 BSEL0 13
Legend: — = unimplemented, read as ‘0’, r = reserved bit. Shaded cells are not used for
power-down.
Note 1: CLKRDY resets to ‘0’ on Power-on Reset but is unaffected on all other Resets.