Datasheet
2006-2012 Microchip Technology Inc. . DS39662E-page 75
ENC28J60
15.0 BUILT-IN SELF-TEST
CONTROLLER
The ENC28J60 features a Built-in Self-Test (BIST)
module which is designed to confirm proper operation
of each bit in the 8-Kbyte memory buffer. Although it is
primarily useful for testing during manufacturing, it
remains present and available for diagnostic purposes
by the user. The controller writes to all locations in the
buffer memory and requires several pieces of hardware
shared by normal Ethernet operations. Thus, the BIST
should only be used on Reset or after necessary
hardware is freed. When the BIST is used, the ECON1
register’s DMAST, RXEN and TXRTS bits should all be
clear.
The BIST controller is operated through four registers:
• EBSTCON register (control and status register)
• EBSTSD register (fill seed/initial shift value)
• EBSTCSH and EBSTCSL registers (high and low
bytes of generated checksum)
The EBSTCON register (Register 15-1) controls the
module’s overall operation, selecting the Testing
modes and starting the self-test process. The bit pat-
tern for memory tests is provided by the EBSTSD seed
register; its content is either used directly, or as the
seed for a pseudo-random number generator,
depending on the Test mode.
REGISTER 15-1: EBSTCON: ETHERNET SELF-TEST CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PSV2 PSV1 PSV0 PSEL TMSEL1 TMSEL0 TME BISTST
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 PSV<2:0>: Pattern Shift Value bits
When TMSEL<1:0> =
10:
The bits in EBSTSD will shift left by this amount after writing to each memory location.
When TMSEL<1:0> =
00, 01 or 11:
This value is ignored.
bit 4 PSEL: Port Select bit
1 = DMA and BIST modules will swap ports when accessing the memory
0 = Normal configuration
bit 3-2 TMSEL<1:0>: Test Mode Select bits
11 = Reserved
10 = Pattern shift fill
01 = Address fill
00 = Random data fill
bit 1 TME: Test Mode Enable bit
1 = Enable Test mode
0 = Disable Test mode
bit 0 BISTST: Built-in Self-Test Start/Busy bit
1 = Test in progress; cleared automatically when test is done
0 = No test running