Datasheet

 2006-2012 Microchip Technology Inc. . DS39662E-page 77
ENC28J60
TABLE 15-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE SELF-TEST CONTROLLER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
ECON1
TXRST RXRST DMAST CSUMEN TXRTS RXEN BSEL1 BSEL0 13
ERXNDL RX End Low Byte (ERXND<7:0>) 13
ERXNDH
— — — RX End High Byte (ERXND<12:8>) 13
EDMASTL DMA Start Low Byte (EDMAST<7:0>) 13
EDMASTH — — — DMA Start High Byte (EDMAST<12:8>) 13
EDMANDL DMA End Low Byte (EDMAND<7:0>) 13
EDMANDH
— — — DMA End High Byte (EDMAND<12:8>) 13
EDMACSL DMA Checksum Low Byte (EDMACS<7:0>) 13
EDMACSH DMA Checksum High Byte (EDMACS<15:8>) 13
EBSTSD Built-in Self-Test Fill Seed (EBSTSD<7:0>) 14
EBSTCON PSV2 PSV1 PSV0 PSEL TMSEL1 TMSEL0 TME BISTST 14
EBSTCSL Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) 14
EBSTCSH Built-in Self-Test Checksum High Byte (EBSTCS<15:8>) 14
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used.