Datasheet

ENC28J60
DS39662E-page 98 .  2006-2012 Microchip Technology Inc.
O
Oscillator ............................................................................... 5
Start-up Timer (OST) ....................................................5
P
Package Types ..................................................................... 1
Packaging Information ........................................................83
Details .........................................................................84
Marking ....................................................................... 83
Per Packet Control Byte Format ......................................... 39
PHID Registers ................................................................... 22
PHSTAT Registers.............................................................. 22
PHY Register Summary ...................................................... 20
PHY Registers..................................................................... 19
Reading....................................................................... 19
Scanning ..................................................................... 19
Writing......................................................................... 19
Pin Diagrams.........................................................................1
Pinout I/O Descriptions ......................................................... 4
Power-Down........................................................................ 73
Associated Registers .................................................. 73
Power-on Reset (POR) ....................................................... 60
R
Read Control Register (RCR) ............................................. 27
Reader Response ............................................................... 96
Receive Filters .................................................................... 47
Broadcast.................................................................... 52
Hash Table.................................................................. 52
Magic Packet .............................................................. 52
Multicast...................................................................... 52
Pattern Match Filter..................................................... 51
Unicast Filter ...............................................................51
Receiving Packets............................................................... 43
Associated Registers .................................................. 46
Calculating Buffer Free Space ....................................45
Calculating Free Receive Buffer Space ...................... 45
Calculating Random Access Address ......................... 44
Enabling Reception.....................................................43
Freeing Buffer Space .................................................. 45
Layout ......................................................................... 43
Reading....................................................................... 44
Status Vectors............................................................. 44
Registers
EBSTCON (Ethernet Self-Test Control)...................... 75
ECOCON (Clock Output Control) .................................6
ECON1 (Ethernet Control 1) ....................................... 15
ECON2 (Ethernet Control 2) ....................................... 16
EFLOCON (Ethernet Flow Control) ............................ 56
EIE (Ethernet Interrupt Enable)...................................65
EIR (Ethernet Interrupt Request, Flag) ....................... 66
ERXFCON (Ethernet Receive Filter Control) .............. 48
ESTAT (Ethernet Status) ............................................ 64
MABBIPG (MAC Back-to-Back Inter-Packet Gap)......36
MACON1 (MAC Control 1).......................................... 34
MACON3 (MAC Control 3).......................................... 35
MACON4 (MAC Control 4).......................................... 36
MICMD (MII Command).............................................. 21
MISTAT (MII Status) ................................................... 21
PHCON1 (PHY Control 1) .......................................... 61
PHCON2 (PHY Control 2) .......................................... 37
PHID (PHY Device ID)................................................ 22
PHIE (PHY Interrupt Enable) ...................................... 67
PHIR (PHY Interrupt Request, Flag)........................... 67
PHLCON (PHY Module LED Control)........................... 9
PHSTAT1 (Physical Layer Status 1)........................... 23
PHSTAT2 (Physical Layer Status 2)........................... 24
Resets................................................................................. 59
MAC, PHY Subsystem................................................ 61
Power-on Reset.......................................................... 60
Receive Only .............................................................. 60
System........................................................................ 60
Transmit Only ............................................................. 60
Revision History.................................................................. 93
S
Serial Peripheral Interface. See SPI.
SPI
Bit Field Clear Command............................................ 29
Bit Field Set Command............................................... 29
Instruction Set............................................................. 26
Overview..................................................................... 25
Read Buffer
Memory Command ............................................. 28
Read Control Register Command............................... 27
System Reset Command............................................ 30
Write Buffer
Memory Command ............................................. 29
Write Control Register Command............................... 28
T
Termination Requirement ..................................................... 7
Timing Diagrams
CLKOUT Transition ...................................................... 6
Read Control Register Command
(ETH Registers).................................................. 27
Read Control Register Command
(MAC/MII Registers) ........................................... 27
SPI Input............................................................... 25, 82
SPI Output ............................................................ 25, 82
System Reset Command Sequence........................... 30
Write Buffer Memory Command Sequence ................ 29
Write Control Register Command Sequence.............. 28
Transmitting Packets .......................................................... 39
Associated Registers.................................................. 42
Status Vectors ............................................................ 41
W
WWW Address ................................................................... 95
WWW, On-Line Support ....................................................... 2