Datasheet

 2016 Microchip Technology Inc. DS00002164B-page 21
LAN8710A/LAN8710AI
In RMII mode, the 2-bit data nibbles are sent to the RMII block. These data nibbles are clocked to the controller at a rate
of 50MHz. The controller samples the data on the rising edge of XTAL1/CLKIN (REF_CLK). To ensure that the setup
and hold requirements are met, the nibbles are clocked out of the transceiver on the falling edge of XTAL1/CLKIN
(REF_CLK).
3.1.3 10BASE-T TRANSMIT
Data to be transmitted comes from the MAC layer controller. The 10BASE-T transmitter receives 4-bit nibbles from the
MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream. The data stream is then Manchester-encoded
and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics.
The 10M transmitter uses the following blocks:
• MII (digital)
• TX 10M (digital)
• 10M Transmitter (analog)
• 10M PLL (analog)
3.1.3.1 10M Transmit Data Across the MII/RMII Interface
The MAC controller drives the transmit data onto the TXD bus. For MII, when the controller has driven TXEN high to
indicate valid data, the data is latched by the MII block on the rising edge of TXCLK. The data is in the form of 4-bit wide
2.5MHz data. For RMII, TXD[1:0] shall transition synchronously with respect to REF_CLK. When TXEN is asserted,
TXD[1:0] are accepted for transmission by the device. TXD[1:0] shall be “00” to indicate idle when TXEN is deasserted.
Values of TXD[1:0] other than “00” when TXEN is deasserted are reserved for out-of-band signaling (to be defined).
Values other than “00” on TXD[1:0] while TXEN is deasserted shall be ignored by the device.TXD[1:0] shall provide valid
data for each REF_CLK period while TXEN is asserted.
In order to comply with legacy 10BASE-T MAC/Controllers, in half-duplex mode the transceiver loops back the trans-
mitted data, on the receive path. This does not confuse the MAC/Controller since the COL signal is not asserted during
this time. The transceiver also supports the SQE (Heartbeat) signal. See Section 3.8.7, "Collision Detect," on page 35,
for more details.
3.1.3.2 Manchester Encoding
The 4-bit wide data is sent to the 10M TX block. The nibbles are converted to a 10Mbps serial NRZI data stream. The
10M PLL locks onto the external clock or internal oscillator and produces a 20MHz clock. This is used to Manchester
encode the NRZ data stream. When no data is being transmitted (TXEN is low), the 10M TX block outputs Normal Link
Pulses (NLPs) to maintain communications with the remote link partner.
3.1.3.3 10M Transmit Drivers
The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered before being driven out
as a differential signal across the TXP and TXN outputs.
3.1.4 10BASE-T RECEIVE
The 10BASE-T receiver gets the Manchester- encoded analog signal from the cable via the magnetics. It recovers the
receive clock from the signal and uses this clock to recover the NRZI data stream. This 10M serial data is converted to
4-bit data nibbles which are passed to the controller via MII at a rate of 2.5MHz.
This 10M receiver uses the following blocks:
• Filter and SQUELCH (analog)
• 10M PLL (analog)
• RX 10M (digital)
• MII (digital)
3.1.4.1 10M Receive Input and Squelch
The Manchester signal from the cable is fed into the transceiver (on inputs RXP and RXN) via 1:1 ratio magnetics. It is
first filtered to reduce any out-of-band noise. It then passes through a SQUELCH circuit. The SQUELCH is a set of
amplitude and timing comparators that normally reject differential voltage levels below 300mV and detect and recognize
differential voltages above 585mV.