Datasheet
Table Of Contents
- Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
- 1.0 Introduction
- 2.0 Pin Description and Configuration
- 3.0 Functional Description
- 3.1 Transceiver
- 3.2 Auto-negotiation
- 3.3 HP Auto-MDIX Support
- 3.4 MAC Interface
- 3.5 Serial Management Interface (SMI)
- 3.6 Interrupt Management
- 3.7 Configuration Straps
- 3.8 Miscellaneous Functions
- 3.9 Application Diagrams
- 4.0 Register Descriptions
- 4.1 Register Nomenclature
- 4.2 Control and Status Registers
- TABLE 4-2: SMI Register Map
- 4.2.1 Basic Control Register
- 4.2.2 Basic Status Register
- 4.2.3 PHY Identifier 1 Register
- 4.2.4 PHY Identifier 2 Register
- 4.2.5 Auto Negotiation Advertisement Register
- 4.2.6 Auto Negotiation Link Partner Ability Register
- 4.2.7 Auto Negotiation Expansion Register
- 4.2.8 Mode Control/Status Register
- 4.2.9 Special Modes Register
- 4.2.10 Symbol Error Counter Register
- 4.2.11 Special Control/Status Indications Register
- 4.2.12 Interrupt Source Flag Register
- 4.2.13 Interrupt Mask Register
- 4.2.14 PHY Special Control/Status Register
- 5.0 Operational Characteristics
- 6.0 Package Information
- 7.0 Application Notes
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
2016 Microchip Technology Inc. DS00002165B-page 29
LAN8720A/LAN8720AI
Note: Because the nINTSEL configuration strap shares functionality with the LED2 pin, proper consideration must
also be given to the LED polarity. Refer to Section 3.8.1.2, "nINTSEL and LED2 Polarity Selection," on
page 33 for additional information on the relation between nINTSEL and the LED2 polarity.
3.7.4.1 REF_CLK In Mode
In REF_CLK In Mode, the 50MHz REF_CLK is driven on the XTAL1/CLKIN pin. A 50MHz source for REF_CLK must
be available external to the device when using this mode. The clock is driven to both the MAC and PHY as shown in
Figure 3-7.
FIGURE 3-7: EXTERNAL 50MHZ CLOCK SOURCES THE REF_CLK
LAN8720A/LAN8720Ai
10/100 PHY
24-QFN
RMII
TXP
TXN
Mag RJ45
RXP
RXN
XTAL1/CLKIN
XTAL2
TXD[1:0]
2
RXD[1:0]
CRS_DV
2
RMII
LED[2:1]
2
Interface
MDIO
MDC
nINT
nRST
TXEN
MAC
Accepts external
50MHz clock
50MHz
Reference
Clock
All RMII signals are
synchronous to the supplied
clock
REF_CLK
RXER
3.7.4.2 REF_CLK Out Mode
To reduce BOM cost, the device includes a feature to generate the RMII REF_CLK signal from a low-cost, 25MHz fun-
damental crystal. This type of crystal is inexpensive in comparison to 3
rd
overtone crystals that would normally be
required for 50MHz. The MAC must be capable of operating with an external clock to take advantage of this feature as
shown in Figure 3-8.
In order to optimize package size and cost, the REFCLKO pin i
s multiplexed with the nINT pin. In REF_CLK Out mode,
the nINT functionality is disabled to accommodate usage of REFCLKO as a 50MHz clock to the MAC.
Note: Th
e REF_CLK Out Mode is not part of the RMII Specification. Timing in this mode is not compliant with the
RMII specification. To ensure proper system operation, a timing analysis of the MAC and LAN8720 must be
performed.