Datasheet

 2016 Microchip Technology Inc. DS00002165B-page 41
LAN8720A/LAN8720AI
4.0 REGISTER DESCRIPTIONS
This chapter describes the various control and status registers (CSRs). All registers follow the IEEE 802.3 (clause
22.2.4) management register set. All functionality and bit definitions comply with these standards. The IEEE 802.3 spec-
ified register index (in decimal) is includ
ed with each register definition, allowing for addressing of these registers via
the Serial Management Interface (SMI) protocol.
4.1 Register Nomenclature
Table 4-1 describes the register bit attribute notation used throughout this document.
TABLE 4-1: REGISTER BIT TYPES
Register Bit Type
Notation
Register Bit Description
R Read: A re
gister or bit with this attribute can be read.
W Read: A re
gister or bit with this attribute can be written.
RO Read only: Read
only. Writes have no effect.
WO Write only:
If a register or bit is write-only, reads will return unspecified data.
WC Write One to Clear: writ
ing a one clears the value. Writing a zero has no effect
WAC Write Anything to Clear: writ
ing anything clears the value.
RC Read to Clear: Co
ntents is cleared after the read. Writes have no effect.
LL Latch Low: C
lear on read of register.
LH Latch High: Clea
r on read of register.
SC Self-Clearing: Cont
ents are self-cleared after the being set. Writes of zero have no
effect. Contents can be read.
SS Self-Setting: Con
tents are self-setting after being cleared. Writes of one have no
effect. Contents can be read.
RO/LH Read Only, Latch High: Bit
s with this attribute will stay high until the bit is read. After it
is read, the bit will either remain high if the high condition remains, or will go low if the
high condition has been removed. If the bit has not been read, the bit will remain high
regardless of a change to the high condition. This mode is used in some Ethernet PHY
registers.
NASR Not Affected by Software Reset. Th
e state of NASR bits do not change on assertion
of a software reset.
RESERVED Reserved Field:
Reserved fields must be written with zeros to ensure future compati-
bility. The value of reserved bits is not guaranteed on a read.
Many of these register bit notations can be combin
ed. Some examples of this are shown below:
• R/
W: Can be written. Will return current setting on a read.
• R/
WAC: Will return current setting on a read. Writing anything clears the bit.
4.2 Control and Status Registers
Table 4-2 provides a list of supported registers. Register details, including bit definitions, are provided in the proceeding
subsections.