Datasheet

 2016 Microchip Technology Inc. DS00002165B-page 61
LAN8720A/LAN8720AI
5.5.4.2 RMII Timing (REF_CLK In Mode)
The 50MHz REF_CLK IN timing applies to the case when nINTSEL is floated or pulled-high. In this mode, a 50MHz
clock must be input on the CLKIN pin. For more information on REF_CLK In Mode, see Section 3.7.4.1, REF_CLK In
Mode.
FIGURE 5-5: RMII TIMING (REF_CLK IN MODE)
CLKIN
(REF_CLK)
RXD[1:0],
RXER
CRS_DV
t
clkh
t
clkl
t
clkp
t
oval
t
ohold
t
oval
t
oval
t
ohold
t
su
TXD[1:0]
TXEN
t
ihold
t
su
t
ihold
t
ihold
t
su
t
ihold
TABLE 5-10: RMII TIMING VALUES (REF_CLK IN MODE)
Symbol Description Min Max Units Notes
t
clkp
CLKIN period 20 — ns —
t
clkh
CLKIN high time t
clkp
*0.35 t
clkp
*0.65 ns —
t
clkl
CLKIN low time t
clkp
*0.35 t
clkp
*0.65 ns —
t
oval
RXD[1:0], RXER, CRS_DV output valid from ris-
ing edge of CLKIN
— 14.0 ns Note 5-25
t
ohold
RXD[1:0], RXER, CRS_DV output hold from ris-
ing edge of CLKIN
3.0 — ns Note 5-25
t
su
TXD[1:0], TXEN setup time to rising edge of
CLKIN
4.0 — ns Note 5-25
t
ihold
TXD[1:0], TXEN input hold time after rising edge
of CLKIN
1.5 — ns Note 5-25
Note 5-25 T
iming was designed for system load between 10 pf and 25 pf.