Datasheet

 2016 Microchip Technology Inc. DS00002165B-page 73
LAN8720A/LAN8720AI
APPENDIX A: DATA SHEET REVISION HISTORY
TABLE A-1: REVISION HISTORY
Revision Section/Figure/Entry Correction
Rev B. (07-15-16) Section 5.1, "Absolute Maxi-
mum Ratings*," on page 54
Update to Positive voltage on XTAL1/CLKIN, with
respe
ct to ground.
Table 5-2, “Non-Variable I/O
Buffer Characteristics,” on
page 56
Update to min/max values for the last row, ICLK
T
ype Buffer (XTAL1 Input) - High Input Level.
Rev. A (06-24-16) All Document converted to Microchip look and feel.
Rep
laces SMSC Rev. 1.4 (08-23-12).
Section 5.2, "Operating Con-
ditions**," on page 54
Increased VDDCR operational limits from “+1.14V
to
+1.26V” to “+1.08V to +1.32V”
Section 5.6, "Clock Circuit,"
on page 65
Added new 100uW crystal specifications and circuit
dia
gram. The section is now split into two subsec-
tions, one for 300uW crystals and the other for
100uW cryst
als.
Section 6.0, "Package Infor-
mation," on page 68
Added new subsections to include SQFN package
information.
Section , "Product Identifica-
tion System," on page 77
Updated ordering codes with sawn SQFN package
options.
Rev. 1.4
(08-23-12)
Section 4.2.2, Basic Status
Register
Updated definitions of bits 10:8.
Rev. 1.3
(04-20-11)
Table 5-9, “RMII Timing Val-
ues (REF_CLK Out Mode),”
on page 60
Updated t
oval
maximum value from 10.0ns to 5.0ns.
Rev. 1.2 (11-10-10) Section 5.5.5, "RMII Inter-
face Timing," on page 63
Updated diagrams and tables to include RXER.