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SMSC LAN91C111 REV C DATASHEET Revision 1.92 (06-27-11)

Datasheet

PRODUCT FEATURES

LAN91C111

10/100 Non-PCI Ethernet

Single Chip MAC + PHY

 Single Chip Ethernet Controller

 Dual Speed - 10/100 Mbps

 Fully Supports Full Duplex Switched Ethernet

 Supports Burst Data Transfer

 8 Kbytes Internal Memory for Receive and Transmit

FIFO Buffers

 Enhanced Power Management Features

 Optional Configuration via Serial EEPROM Interface

 Supports 8, 16 and 32 Bit CPU Accesses

 Internal 32 Bit Wide Data Path (Into Packet Buffer

Memory)

 Built-in Transparent Arbitration for Slave Sequential

Access Architecture

 Flat MMU Architecture with Symmetric Transmit and

Receive Structures and Queues

 3.3V Operation with 5V Tolerant IO Buffers (See Pin

List Description for Additional Details)

 Single 25 MHz Reference Clock for Both PHY and

MAC

 External 25Mhz-output pin for an external PHY

supporting PHYs physical media.

 Low Power CMOS Design

 Supports Multiple Embedded Processor Host

Interfaces

—ARM

—SH

— Power PC

— Coldfire

— 680X0, 683XX

— MIPS R3000

 3.3V MII (Media Independent Interface) MAC-PHY

Interface Running at Nibble Rate

 MII Management Serial Interface

 128-Pin QFP lead-free RoHS compliant package

 128-Pin TQFP 1.0 mm height lead-free RoHS

compliant package

 Commercial Temperature Range from 0°C to 70°C

(LAN91C111)

 Industrial Temperature Range from -40°C to 85°C

(LAN91C111i)

Network Interface

 Fully Integrated IEEE 802.3/802.3u-100Base-TX/

10Base-T Physical Layer

 Auto Negotiation: 10/100, Full / Half Duplex

 On Chip Wave Shaping - No External Filters

Required

 Adaptive Equalizer

 Baseline Wander Correction

 LED Outputs (User selectable – Up to 2 LED

functions at one time)

—Link

—Activity

— Full Duplex

— 10/100

— Transmit

— Receive

Summary of content (133 pages)

PAGE 1
LAN91C111 10/100 Non-PCI Ethernet Single Chip MAC + PHY PRODUCT FEATURES Datasheet Single Chip Ethernet Controller Dual Speed - 10/100 Mbps Fully Supports Full Duplex Switched Ethernet Supports Burst Data Transfer 8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers Enhanced Power Management Features Optional Configuration via Serial EEPROM Interface Supports 8, 16 and 32 Bit CPU Accesses Internal 32 Bit Wide Data Path (Into Packet Buffer Memory) Built-in
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Order Numbers: LAN91C111-NS, LAN91C111i-NS (Industrial Temperature) for 128-Pin QFP Lead-free RoHS Compliant packages LAN91C111-NU (1.0mm height); LAN91C111i-NU (Industrial Temperature) for 128-pin TQFP Lead-free RoHS Compliant packages This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit www.smsc.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table of Contents Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 2 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 4 Signal Descriptions . . . . . . . .
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 8.25 8.26 Receive Frame Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bank Select Register . . . . . . . . . . . . . . . . .
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 14 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Chapter 15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Chapter 16 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 SMSC LAN91C111 REV C 5 DATASHEET Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet List of Figures Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2.2 Pin Configuration - LAN91C111-FEAST 128 PIN QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3.1 Basic Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3.2 Block Diagram . . . . . . . . . . . . . . . . . . .
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet List of Tables Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package) . . . . . . . . . . . . . . 14 Table 7.1 4B/5B Symbol Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 7.2 Transmit Level Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 8.1 Internal I/O Space Mapping . . . . . .
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 1 General Description The SMSC LAN91C111 is designed to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design requirements. The LAN91C111 is a mixed signal Analog/Digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 2 Pin Configurations 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 XTAL2 XTAL1 RX_ER RX_DV RXD0 RXD1 RXD2 RXD3 VDD CRS100 RX25 GND TXD0 TXD1 TXD2 TXD3 COL100 TXEN100 VDD TX25 GND D0 D1 D2 D3 GND D4 D5 D6 D7 VDD nBE3 Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 LAN91C111FEASTTM 128 PIN TQFP 96 95 94 93
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/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 RX_ER RX_DV RXD0 RXD1 RXD2 RXD3 VDD CRS100 RX25 GND TXD0 TXD1 TXD2 TXD3 COL100 TXEN100 VDD TX25 GND D0 D1 D2 D3 GND D4 D5 Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 LAN91C111FEASTTM 128 PIN QFP 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 3 Block Diagrams The diagram shown in Figure 3.1, "Basic Functional Block Diagram", describes the device basic functional blocks. The SMSC LAN91C111 is a single chip solution for embedded designs with minimal Host and external supporting devices required to implement 10/100 Ethernet connectivity solutions.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet EEPROM INTERFACE MII Control Control Control Control Address 8-32 bit Bus Interface Unit Control Arbiter Control TPO Control WR FIFO Data RD FIFO MMU Ethernet Protocol Handler (EPH) DMA TX/RX FIFO Pointer TX Data 8K Byte Dynamically Allocated SRAM 10/100 PHY TXD[0-3] 32-bit Data 32-bit Data TPI RX Data RXD[0-3] Figure 3.2 Block Diagram The diagram shown in Figure 3.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet EECS EESK EEDO EEDI MII External Signals RBIAS EEPROM CONTROL To MII External Signals 4B5B ENCODER MLT3 ENCODER SCRAMBLER LP FILTER + TPO+ - TPO- CLOCK GEN (PLL) 10BASE-T TRANSMITTER MANCHESTER CRS100 COL100 ROM DAC + LP FILTER - CLOCK GEN (PLL) COLLISION RXD[3:0] RX_ER RX_DV RX25 SQUELCH 4B5B DECODER MII SERIAL Manage -ment SWITCHED CURRENT SOURCE CLOCK & DATA RECOVERY DESCRAMBL ER 100BASE-TX RECEIVER +/- Vth MLT ENCODER
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 4 Signal Descriptions Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 5 Description of Pin Functions PIN NO. NAME SYMBOL BUFFER TYPE DESCRIPTION TQFP QFP 81-92 83-94 Address A4-A15 I** Input. Decoded by LAN91C111 to determine access to its registers. 78-80 80-82 Address A1-A3 I** Input. Used by LAN91C111 for internal register selection. 41 43 Address Enable AEN I** Input. Used as an address qualifier. Address decoding is only enabled when AEN is low.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PIN NO. NAME BUFFER TYPE SYMBOL DESCRIPTION TQFP QFP 42 44 Local Bus Clock LCLK I** Input. Used to interface synchronous buses. Maximum frequency is 50 MHz. Limited to 8.33 MHz for EISA DMA burst mode. This pin should be tied high if it is in asynchronous mode. 38 40 Asynchronous Ready ARDY OD16 Open drain output. ARDY may be used when interfacing asynchronous buses to extend accesses.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PIN NO. NAME SYMBOL BUFFER TYPE DESCRIPTION TQFP QFP 9 11 EEPROM Clock EESK O4 Output. 4 μsec clock used to shift data in and out of the serial EEPROM. 10 12 EEPROM Select EECS O4 Output. Serial EEPROM chip select. Used for selection and command framing of the serial EEPROM. 7 9 EEPROM Data Out EEDO O4 Output. Connected to the DI input of the serial EEPROM. 8 10 EEPROM Data In EEDI I with Input.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PIN NO. NAME SYMBOL BUFFER TYPE DESCRIPTION TQFP QFP 125 127 Receive Data Valid RX_DV I with pulldown Input from MII PHY. Envelope of data valid reception. Used for receive data framing. 112 114 Collision Detect 100 Mbps COL100 I with pulldown Input from MII PHY. Collision detection input. 113-116 115-118 Transmit Data TXD3TXD0 O12 Outputs. Transmit Data nibble to MII PHY. 109 111 Transmit Clock TX25 I with pullup Input.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 6 Signal Description Parameters This section provides a detailed description of each SMSC LAN91C111 signal. The signals are arranged in functional groups according to their associated function. The ‘n’ symbol at the beginning of a signal name indicates that it is an active low signal. When ‘n’ is not present before the signal name, it indicates an active high signal.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 7 Functional Description 7.1 Clock Generator Block 1. The XTAL1 and XTAL2 pins are to be connected to a 25 MHz crystal. 2. TX25 is an input clock. It will be the nibble rate of the particular PHY connected to the MII (2.5 MHz for a 10 Mbps PHY, and 25 MHz for a 100 Mbps PHY). 3. RX25 - This is the MII nibble rate receive clock used for sampling received data nibbles and running the receive state machine. (2.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 7.4 BIU Block The Bus Interface Unit can handle synchronous as well as asynchronous buses; different signals are used for each one. Transparent latches are added on the address path using rising nADS for latching. When working with an asynchronous bus like ISA, the read and write operations are controlled by the edges of nRD and nWR. ARDY is used for notifying the system that it should extend the access cycle.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet from the PHY registers. Timing and framing for each management command is to be generated by the CPU (host). The MAC and external PHY communicate via MDIO and MDC of the MII Management serial interface. MDIO:Management Data input/output. Bi-directional between MAC and PHY that carries management data. All control and status information sent over this pin is driven and sampled synchronously to the rising edge of MDC signal. MDC:Management Data Clock.
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SMSC LAN91C111 REV C 23 DATASHEET MDIO MDC MDIO MDC ST[1:0] 0 0 READ CYCLE ST[1:0] 0 0 WRITE CYCLE 1 1 1 1 OP[1:0] 1 2 OP[1:0] 0 2 0 1 3 3 P4 P3 P2 6 PHYAD[4:0] P2 6 PHYAD[4:0] 5 P3 5 P1 7 P1 7 P0 8 P0 8 R4 9 R4 9 R3 R2 11 12 R1 REGAD[4:0] R2 11 R1 12 R0 13 1 15 0 TA[1:0] 14 D15 16 D14 17 D13 18 R0 13 TA[1:0] Z 14 0 15 D15 16 D14 17 D13 18 WRITE BITS PHY CLOCKS IN DATA ON RISING EDGES OF MDC REGAD[4:0] 10 R3 10 WRITE
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 7.5.4 MII Packet Data Communication with External PHY The MIl is a nibble wide packet data interface defined in IEEE 802.3. The LAN91C111 meets all the MIl requirements outlined in IEEE 802.3 and shown in Figure 7.2. TX_EN = 1 TX_EN = 0 TX_EN = 0 START IDLE PREAMBLE OF FRAME DELIM. PRMBLE SFD 62 BT 2 BT IDLE DATA NIBBLES DATA 1 DATA 2 DATA N-1 DATA N PREAMBLE = [ 1 0 1 0 ...
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet beyond a full flag octet for reception. RX_DV as well as RXD0-RXD3 are sampled on RX25 rising edges. RXD0 carries the least significant bit and RXD3 the most significant bit of the nibble. RX_DV goes inactive when the last valid nibble of the packet (CRC) is presented at RXD0-RXD3. RX_ER might be asserted during packet reception to signal the LAN91C111 that the present receive packet is invalid.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet ETHERNET MAC FRAME INTERFRAME GAP SFD PREAMBLE DA SA LN LLC DATA FCS LN LLC DATA FCS INTERFRAME GAP 100 BASE-TX DATA SYMBOLS IDLE SSD DA SFD PREAMBLE IDLE SSD SA ESD IDLE SOI IDLE = [ 1 1 1 1...] = [ 1 1 0 0 0 1 0 0 0 1] BEFORE / AFTER 4B5B ENCODING, SCRAMBLING, AND MLT3 CODING PREAMBLE = [ 1 0 1 0 ...
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 7.7.1 MII Disable The internal PHY MII interface can be disabled by setting the MII disable bit in the MI serial port Control register. When the MII is disabled, the MII inputs are ignored, the MII outputs are placed in high impedance state, and the TP output is high impedance. 7.7.2 Encoder 4B5B Encoder - 100 Mbps 100BASE-TX requires that the data be 4B5B encoded. 4B5B coding converts the 4-Bit data nibbles into 5-Bit date code words.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 7.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Data Recovery - 100 Mbps Data recovery is performed by latching in data from the TP receiver with the recovered clock extracted by the PLL. The data is then converted from a single bit stream into nibble wide data word according to the format shown in Figure 7.2. Clock Recovery - 10 Mbps The clock recovery process for 10Mbps mode is identical to the 100Mbps mode except, (1) the recovered clock frequency is 2.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 10 Mbps A descrambler is not used in 10 Mbps mode. Descrambler Bypass The descrambler can be bypassed by setting the bypass scrambler/descrambler bit in the PHY MI serial port Configuration 1 register. When this bit is set, the data bypasses the descrambler and goes directly from the TP receiver to the 4B5B decoder. 7.7.7 Twisted Pair Transmitter Transmitter - 100 Mbps The TX transmitter consists of MLT-3 encoder, waveform generator and line driver.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet N B 1.0 0.8 P H 0.6 D 0.4 C I O E Voltage (V) 0.2 0.0 Q A M F R J -0.2 S -0.4 U LK -0.6 W V -0.8 G -1.0 0 10 20 30 40 50 60 70 80 90 100 T 10 TIME (ns) Figure 7.4 TP Output Voltage Template - 10 MBPS REFERENCE TIME (NS) INTERNAL MAU VOLTAGE (V) A 0 0 B 15 1.0 C 15 0.4 D 25 0.55 E 32 0.45 F 39 0 G 57 -1.0 H 48 0.7 I 67 0.6 J 89 0 K 74 -0.55 L 73 -0.55 M 61 0 N 85 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet REFERENCE TIME (NS) INTERNAL MAU VOLTAGE (V) P 110 0.75 Q 111 0.15 R 111 0 S 111 -0.15 T 110 -1.0 U 100 -0.3 V 110 -0.7 W 90 -0.7 Transmit Level Adjust The transmit output current level is derived from an internal reference voltage and the external resistor on RBIAS pin.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Transmit Rise and Fall Time Adjust The transmit output rise and fall time can be adjusted with the two transmit rise/fall time adjust bits in the PHY Ml serial port Configuration 1. The adjustment range is -0.25ns to +0.5ns in 0.25ns steps. STP (150 Ohm) Cable Mode The transmitter can be configured to drive 150 Ohm shielded twisted pair cable.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet a. Short Bit 3.1V Slope 0.5 V/ ns 585mV 585 mV sin ( *t/PW) PW 0 b. Long Bit 3.1V Slope 0.5 V/ ns 585mV 585 mV sin (2 * t/PW) 585 mV sin [2 3PW/4 PW/4 0 (t - PW/2)/PW] PW Figure 7.5 TP Input Voltage Template -10MBPS TP Squelch - 100 Mbps The squelch block determines if the TP input contains valid data. The 100 Mbps TP squelch is one of the criteria used to determine link integrity.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet a CRS100 is asserted, and (6) the receiver meets the squelch requirements defined in IEEE 802.3 Clause 14. Equalizer Disable The adaptive equalizer can be disabled by setting the equalizer disable bit in the PHY Ml serial port Configuration 1 register. When disabled, the equalizer is forced into the response it would normally have if zero cable length was detected. Receive Level Adjust The receiver squelch and unsquelch levels can be lowered by 4.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of the /J/K/ symbols, the start of packet is detected, data reception is begun, the MAC is notified that valid data is received, and 5/5/ symbols are substituted in place of the /J/K/ symbols.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 0 BT 4.5 BT 3.1 V 0.5 V/ns 0.25 BT 2.25 BT 585 mV 6.0 BT +50 mV -50 mV 45.0 BT 585 mV sin(2 * * (t/1BT)) 0 t 0.25 BT and 2.25 t 2.5 BT -3.1 V 2.5 BT 4.5 BT Figure 7.6 SOI Output Voltage Template - 10MBPS 7.7.12 Link Integrity & AutoNegotiation General The LAN91C111 can be configured to implement either the standard link integrity algorithms or the AutoNegotiation algorithm.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 1.3 BT 0 BT 3.1 V 0.5 V/ns 585 mV 0.5 BT 0.6 BT 2.0 BT 300 mV 4.0 BT +50 mV +50 mV -50 mV 0.25 BT 200 mV -50 mV 4.0 BT 42.0 BT -3.1 V 0.85 BT 2.0 BT Figure 7.7 Link Pulse Output Voltage Template - NLP, FLP 100BASE-TX Link Integrity Algorithm -100Mbps Since 100BASE-TX is defined to have an active idle signal, then there is no need to have separate link pulses like those defined for 10BASE-T.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet a.) Normal Link Pulse (NLP) TPO± b.) Fast Link Pulse (FLP) TPO± D0 Clock D1 Clock Data D2 Clock Data D3 Clock Data D14 Clock Data D15 Clock Data Clock Data Figure 7.8 NLP VS. FLP Link Pulse The AutoNegotiation algorithm is initiated by any of these events: (1) AutoNegotiation enabled, (2) a device enters the Link Fail State, (3) AutoNegotiation Reset.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet AutoNegotiation Enable The AutoNegotiation algorithm can be enabled by setting both the ANEG bit in the MAC Receive/PHY Control Register and the ANEG_EN bit in the MI PHY Register 0 (Control register). Clearing either of these two bits will turn off AutoNegotiation mode.
PAGE 41
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet The LAN91C111 will automatically correct for the reverse polarity condition provided that the autopolarity feature is not disabled. Note: The first 3 received packets must be discarded after the correction of a reverse polarity condition. Autopolarity Disable The autopolarity feature can be disabled by setting the autopolarity disable bit in the PHY MI serial port Configuration 2 register. 7.7.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet is then in isolation mode (MII_DIS bit is set); This MII_DIS bit is needed to be cleared. The device is guaranteed to be ready for normal operation 500mS after powerdown is de-asserted. Note: The PDN bit must not be set when the device is in external PHY mode. 7.7.18 PHY Interrupt The LAN91C111 PHY has interrupt capability. The interrupt is triggered by certain output status bits (also referred to as interrupt bits) in the serial port.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 8 MAC Data Structures and Registers 8.1 Frame Format In Buffer Memory The frame format in memory is similar for the Transmit and Receive areas. The first word is reserved for the status word. The next word is used to specify the total number of bytes, and it is followed by the data area. The data area holds the frame itself. By default, the last byte in the receive frame format is followed by the CRC, and the Control byte follows the CRC.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet BYTE COUNT - Divided by two, it defines the total number of words including the STATUS WORD, the BYTE COUNT WORD, the DATA AREA, the CRC, and the CONTROL BYTE. The CRC is not included if the STRIP_CRC bit is set. The maximum number of bytes in a RAM page is 2048 bytes. The receive byte count always appears as even; the ODDFRM bit of the receive status word indicates if the low byte of the last word is relevant.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.2 Receive Frame Status This word is written at the beginning of each receive frame in memory. It is not available as a register. HIGH BYTE ALGN ERR BROD CAST BAD CRC LOW BYTE ODD FRM TOOLNG TOO SHORT HASH VALUE Reserved 5 4 3 MULT CAST 2 1 0 ALGNERR - Frame had alignment error. BROADCAST - Receive frame was broadcast.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.3 I/O Space The base I/O space is determined by the IOS0-IOS2 inputs and the EEPROM contents. To limit the I/O space requirements to 16 locations, the registers are assigned to different banks. The last word of the I/O area is shared by all banks and can be used to change the bank in use.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.4 HIGH BYTE Bank Select Register OFFSET NAME TYPE SYMBOL E BANK SELECT REGISTER READ/WRITE BSR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 1 1 0 0 1 1 BS2 BS1 BS0 0 0 0 LOW BYTE X X X X X BS2, BS1, BS0 Determine the bank presently in use. This register is always accessible and is used to select the register bank in use.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.5 Bank 0 - Transmit Control Register OFFSET NAME TYPE SYMBOL 0 TRANSMIT CONTROL REGISTER READ/WRITE TCR This register holds bits programmed by the CPU to control some of the protocol transmit options.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet the line. If a packet is queued, a preamble and SFD will be transmitted. This bit defaults low to normal operation. NOTE: The LATCOL bit in the EPHSR, setting up as a result of FORCOL, will reset TXENA to 0. In order to force another collision, TXENA must be set to 1 again. LOOP - Loopback. General purpose output port used to control the LBK pin. Typically used to put the PHY chip in loopback mode. TXENA - Transmit enabled when set.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SQET - Signal Quality Error Test. This bit is set under the following conditions: 1. LAN91C111 is set to operate in Half Duplex mode (SWFDUP=0); 2. When STP_SQET=1 and SWFDUP=0, SQET bit will be set upon completion of a transmit operation and no SQET Pulse has occurred during the IPG (Inter Frame Gap). If a pulse has occurred during the IPG, SQET bit will not get set. 3.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet ABORT_ENB - Enables abort of receive when collision occurs. Defaults low. When set, the LAN91C111 will automatically abort a packet being received when the appropriate collision input is activated. This bit has no effect if the SWFDUP bit in the TCR is set. STRIP_CRC - When set, it strips the CRC on received frames. As a result, both the Byte Count and the frame format do not contain the CRC.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.9 Bank 0 - Memory Information Register OFFSET NAME TYPE SYMBOL 8 MEMORY INFORMATION REGISTER READ ONLY MIR HIGH BYTE FREE MEMORY AVAILABLE (IN BYTES * 2K * M) 0 0 0 LOW BYTE 0 0 1 0 0 1 0 0 MEMORY SIZE (IN BYTES *2K * M) 0 0 0 0 0 FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free memory.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet DPLX – Duplex Select - This bit selects Full/Half Duplex operation. This bit is valid and selects duplex operation only when the ANEG Bit = 0, this bit overrides the DPLX bit in the PHY Register 0 (Control Register) and determine the duplex mode. When this bit is set (1), the Internal PHY will operate at full duplex mode. When this bit is cleared (0), the Internal PHY will operate at half Duplex mode.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet WHAT DO YOU WANT TO DO? 100 Half Duplex 10 Full Duplex 10 Half Duplex AUTO-NEGOTIATION CONTROL BITS SPEED AND DUPLEX MODE CONTROL FOR THE PHY DUPLEX MODE CONTROL FOR THE MAC 0 0 1 0 X X 0 0 1 1 0 X X 0 1 0 X X 1 0 0 0 0 0 1 X X 1 0 1 0 1 X X 1 1 0 X X 0 1 1 0 0 0 0 X X 0 0 1 0 0 X X 0 1 0 X X 0 0 0 LS2A, LS1A, LS0A – LED select Signal Enable.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet LS2B LS1B LS0B LED SELECT SIGNAL – LEDB 1 0 0 nPLED2 – Transmit or Receive packet occurred 1 0 1 nPLED3 - 100Mbps Link detected 1 1 0 nPLED4 - Receive packet occurred 1 1 1 nPLED5 - Transmit packet occurred Reserved – Must be 0. 8.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet When this bit is cleared (0 - Default): a. The internal PHY is enabled. b. The external MII pins, including the MII Management interface pins are tri-stated. Reserved – Reserved bits. 8.12 Bank 1 - Base Address Register OFFSET NAME TYPE SYMBOL 2 BASE ADDRESS REGISTER READ/WRITE BAR This register holds the I/O address decode option chosen for the LAN91C111. It is part of the EEPROM saved setup and is not usually modified during run-time.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.13 Bank 1 - Individual Address Registers OFFSET NAME TYPE SYMBOL 4 THROUGH 9 INDIVIDUAL ADDRESS REGISTERS READ/WRITE IAR These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or EEPROM reload. The registers can be modified by the software driver, but a STORE operation will not modify the EEPROM Individual Address contents.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.14 Bank 1 - General Purpose Register OFFSET NAME TYPE SYMBOL A GENERAL PURPOSE REGISTER READ/WRITE GPR HIGH BYTE HIGH DATA BYTE 0 0 0 0 LOW BYTE 0 0 0 0 0 0 0 LOW DATA BYTE 0 0 0 0 0 This register can be used as a way of storing and retrieving non-volatile information in the EEPROM to be used by the software driver.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet transmitted (TX EMPTY INT will be set), or when a packet in the sequence experiences a fatal error (TX INT will be set). Upon a fatal error TXENA is cleared and the transmission sequence stops. The packet number that failed, is present in the FIFO PORTS register, and its pages are not released, allowing the CPU to restart the sequence after corrective action is taken. LE ENABLE - Link Error Enable.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.16 Bank 2 - MMU Command Register OFFSET NAME TYPE SYMBOL 0 MMU COMMAND REGISTER WRITE ONLY BUSY BIT READABLE MMUCR This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet OPERATION CODE DECIMAL VALUE 110 6 ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a packet just loaded into RAM. The packet number to be enqueued is taken from the PACKET NUMBER REGISTER. 111 7 RESET TX FIFOs - This command will reset both TX FIFOs: The TX FIFO holding the packet numbers awaiting transmission and the TX Completion FIFO.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.17 Bank 2 - Packet Number Register OFFSET NAME TYPE SYMBOL 2 PACKET NUMBER REGISTER READ/WRITE PNR Reserved Reserved 0 0 PACKET NUMBER AT TX AREA 0 0 0 0 0 0 PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible through the TX area. Some MMU commands use the number stored in this register as the packet number parameter.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.18 Bank 2 - FIFO Ports Register OFFSET NAME TYPE SYMBOL 4 FIFO PORTS REGISTER READ ONLY FIFO This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The packet numbers to be processed by the interrupt service routines are read from this register.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.19 Bank 2 - Pointer Register OFFSET 6 HIGH BYTE NAME TYPE SYMBOL POINTER REGISTER READ/WRITE NOT EMPTY IS A READ ONLY BIT PTR RCV AUTO INCR. READ Reserved NOT EMPTY 0 0 0 0 0 LOW BYTE POINTER HIGH 0 0 0 0 0 0 POINTER LOW 0 0 0 0 0 POINTER REGISTER - The value of this register determines the address to be accessed within the transmit or receive areas.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.20 Bank 2 - Data Register OFFSET NAME TYPE SYMBOL 8 THROUGH BH DATA REGISTER READ/WRITE DATA DATA HIGH X X X X X X X X X X X X DATA LOW X X X X DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer register.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet These bits automatically latch upon changing state and stay latched until they are read. When they are read, the bits that caused the interrupt to happen are updated to their current value. The MDINT bit will be cleared by writing the acknowledge register with MDINT bit set. Reserved - Must be 0 EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible special conditions.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet TX INT - Set when at least one packet transmission was completed or any of the below transmit fatal errors occurs: SQET - SQE Error LOST CARR - Lost Carrier LATCOL - Late Collision 16COL - 16 collisions The first packet number to be serviced can be read from the FIFO PORTS register. The TX INT bit is always the logic complement of the TEMPTY bit in the FIFO PORTS register.
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SMSC LAN91C111 REV C 69 DATASHEET EPHSR INTERRUPTS MERGED INTO EPH INT TX_SVC TXENA TEMASK CRMASK CTR-ROL LEMASK Edge Detector on Link Err SQET LOST CARR LATCOL 16COL Fatal TX Error TX Complete nWRACK IntAck7 IntAck4 IntAck2 IntAck1 nRDIST nQ D S Q MDINT nQ D S Q RX_OVRN ALLOCATION FAILED nQ D S Q TX FIFO EMPTY nQ D S Q 6 5 4 3 2 1 0 DATA BUS D[15:0] OE D[7:0] Interrupt Status Register 7 RCV FIFO NOT EMPTY 7 6 5 4 3 2 1 0 nOE D[15:8] Interrupt Mask Registe
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet memory structure, the search is limited to comparing only the multicast addresses that have the actual hash value in question. 8.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.24 Bank 3 - Revision Register OFFSET NAME TYPE SYMBOL A REVISION REGISTER READ ONLY REV HIGH BYTE 0 0 LOW BYTE 1 1 0 0 CHIP 1 0 1 1 1 0 REV 0 1 0 0 CHIP - Chip ID. Can be used by software drivers to identify the device used. REV - Revision ID. Incremented for each revision of a given device. 8.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.26 Bank 7 - External Registers OFFSET NAME TYPE 0 THROUG H7 EXTERNAL REGISTERS SYMBOL nCSOUT is driven low by the LAN91C111 when a valid access to the EXTERNAL REGISTER range occurs. HIGH BYTE EXTERNAL R/W REGISTER LOW BYTE EXTERNAL R/W REGISTER CYCLE NCSOUT LAN91C111 DATA BUS AEN=0 A3=0 A4-15 matches I/O BASE BANK SELECT = 7 Driven low. Transparently latched on nADS rising edge. Ignored on writes. Tri-stated on reads.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 9 PHY MII Registers Multiple Register Access Multiple registers can be accessed on a single PHY Ml serial port access cycle with the multiple register access features. The multiple register access features can be enabled by setting the multiple register access enables bit in the PHY Ml serial port Configuration 2 register.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet REGISTER ADDRESS REGISTER NAME 16 Configuration 1 17 Configuration 2 18 Status Output 19 Mask 20 Reserved PHY Register Description Table 9.1 MII Serial Frame Structure
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SYMBOL NAME DEFINITION R/W PHYAD[4:0] Physical Device Address PHYSICAL ADDRESS R REGAD[4:0] Register Address If REGAD[4:0] = 00000-11110, these bits determine the specific register from which D[15:0] is read/written. If multiple register access is enabled and REGAD[4:0] = 11111, all registers are read/written in a single cycle.
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SMSC LAN91C111 REV C 4 77 DATASHEET Reserved Mask 19 20 Status Output 18 17 Configuration 2 16 Configuration 1 AutoNegot. Remote Capability AutoNegot.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 9.1 Register 0. Control Register RST LPBK SPEED ANEG_EN PDN MII_DIS ANEG_RST DPLX RW, SC RW RW RW RW RW RW. SC RW 0 0 1 1 0 1 0 0 COLST Reserved Reserved Reserved Reserved Reserved Reserved Reserved RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 RST - Reset A ‘1’ written to this bit will initiate a reset of the PHY.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet clearing and the PHY will return a ‘1’ until ANEG is initiated, writing a ‘0’ does not affect the ANEG process. DPLX - Duplex mode When Auto Negotiation is disabled this bit can be used to manually select the link duplex state. Writing a ‘1’ to this bit selects full duplex while a ‘0’ selects half duplex. When Auto-Negotiation is enabled reading or writing this bit has no effect.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet ANEG_ACK - Auto-Negotiation Acknowledgment When read as ‘1’ indicate ANEG has been completed and that contents in registers 4,5,6 and 7 are valid. ‘0’ means ANEG has not completed and contents in registers 4,5,6 and 7 are meaningless. The PHY returns zero if ANEG is disabled. REM_FLT- Remote Fault Detect ‘1’ indicates a Remote Fault. Latches the ‘1’ condition and is cleared by reading this register or resetting the PHY.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet TX_HDX 10_FDX 10_HDX Reserved Reserved Reserved Reserved CSMA RW RW RW RW RW RW RW RW 1 1 1 0 0 0 0 1 This register control the values transmitted by the PHY to the remote partner when advertising its abilities NP - Next Page A ‘1’ indicates the PHY wishes to exchange Next Page information.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet TX_HDX 10_FDX 10_HDX Reserved Reserved Reserved Reserved CSMA R R R R R R R R 0 0 0 0 0 0 0 0 The bit definitions are analogous to the Auto Negotiation Advertisement Register. 9.6 Register 16.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Reception Disable idle on powerup and various instances 0 = Enables AutoNegotiation with devices that transmit unscrambled idle on powerup and various instances EQLZR: CABLE Receive Equalizer 1 = Receive Equalizer Disabled, Set To 0 Length Select 0 = Receive Equalizer On (For 100MB Mode Only) Cable Type Select 1 = STP (150 Ohm) 0 = UTP (100 Ohm) RLVL0 TLVL0-3 Receive Input 1 = Receive Squelch Levels Reduced By 4.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet APOLDIS: Auto Polarity Disable JABDIS: Jabber Disable Select MREG: Multiple Register Access Enable INTMDIO: Interrupt Scheme Select Reserved: 9.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet INT: Interrupt Detect 1 = Interrupt Bit(s) Have Changed Since Last Read Operation.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 9.9 Register 19.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 0 = No Mask MSPDDT: Interrupt Mask 100/10 Speed Detect 1 = Mask Interrupt For SPDDET In Register 18 0 = No Mask MDPLDT: Interrupt Mask Duplex Detect 1 = Mask Interrupt For DPLXDET In Register 18 0 = No Mask Reserved: 9.10 Reserved Reserved for Factory Use Register 20.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 10 Software Driver and Hardware Sequence Flow 10.1 Software Driver and Hardware Sequence Flow for Power Management This section describes the sequence of events and the interaction between the Host Driver and the Ethernet controller to perform power management. The Ethernet controller has the ability to reduce its power consumption when the Device is not required to receive or transmit Ethernet Packets.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 10.1 Typical Flow Of Events For Placing Device In Low Power Mode (continued) S/W DRIVER CONTROLLER FUNCTION 9 Ethernet MAC gates the RX Clock, TX clock derived from the Internal PHY. The EPH Clock is also disabled. 10 The Ethernet MAC is now in low power mode. The Host may access all Runtime IO mapped registers. All IO registers are still accessible.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet S/W DRIVER MAC SIDE 3 LOAD TRANSMIT DATA - Copy the TX packet number into the Packet Number Register. Write the Pointer Register, then use a block move operation from the upper layer transmit queue into the Data Register. 4 ISSUE "ENQUEUE PACKET NUMBER TO TX FIFO" - This command writes the number present in the Packet Number Register into the TX FIFO. The transmission is now enqueued.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet S/W DRIVER 4 MAC SIDE ISSUE "ENQUEUE PACKET NUMBER TO TX FIFO" - This command writes the number present in the Packet Number Register into the TX FIFO. The transmission is now enqueued. No further CPU intervention is needed until a transmit interrupt is generated. 5 The enqueued packet will be transferred to the MAC block as a function of TXENA (nTCR) bit and of the deferral process (1/2 duplex mode only) state.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet S/W DRIVER MAC SIDE 4 5 When the end of packet is detected, the status word is placed at the beginning of the receive packet in memory. Byte count is placed at the second word. If the CRC checks correctly the packet number is written into the RX FIFO. The RX FIFO, being not empty, causes RCV INT (interrupt) to be set. The RCV_BAD bit of the Bank 1 Control Register controls whether or not to generate interrupts when bad CRC packets are received.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet ISR Save Bank Select & Address Ptr Registers Mask SMC91C111 Interrupts Read Interrupt Register No Yes RX INTR? Yes TX INTR? Call TX INTR or TXEMPTY INTR No Call RXINTR Get Next TX Yes ALLOC INTR? Packet Available for Transmission? No Yes Write Allocated Pkt # into Packet Number Reg. No Call ALLOCATE Write Ad Ptr Reg.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet RX INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM Yes Destination Multicast? No Read Words 2, 3, 4 from RAM for Address Filtering No No Address Filtering Pass? Status Word OK? Yes Yes Do Receive Lookahead Get Copy Specs from Upper Layer No Okay to Copy? Yes Copy Data Per Upper Layer Specs Issue "Remove and Release" Command Return to ISR Figure 10.2 RX INTR Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet TX Interrupt With AUTO_RELEASE = FALSE 1. Save the Packet Number Register Saved_PNR = Read Byte (Bank 2, Offset 2) 2. Read the EPH Status Register Temp = Read (Bank 0, Offset 2) 3. Acknowledge TX Interrupt Write Byte (0x02, (Bank 2, Offset C)); 4. Check for Status of Transmission If ( Temp AND 0x0001) { //If Successful Transmission Step 4.1.1: Issue MMU Release (Release Specific Packet) Write (0x00A0, (Bank2, Offset 0)); Step 4.1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR TXEMPTY = 0 & TXINT = 0 (Waiting for Completion) TXEMPTY = X & TXINT = 1 (Transmission Failed) TXEMPTY = 1 & TXINT = 0 (Everything went through successfully) Read Pkt.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet D R IV E R S E N D A L L O C ATE C h o o se B a n k S e le ct R e g iste r 2 Issu e "A llo ca te M e m o ry" C o m m a n d to M M U C a ll A L L O C ATE R e a d In te rru p t S ta tu s R e g iste r E xit D rive r S e n d Ye s A llo ca tio n Pa sse d ? No R e a d A llo ca tio n R e su lt R e g iste r W rite A llo ca te d Pa cke t in to Pa cke t # R e g iste r S to re D a ta B u ffe r Po in te r W rite A d d re ss Po in te r R e g iste r C
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet process requests will be dependent on network traffic, in particular on the arrival of broadcast and multicast packets that might not be for the node, and that are not subject to upper layer software flow control. INTERRUPT GENERATION The interrupt strategy for the transmit and receive processes is such that it does not represent the bottleneck in the transmit and receive queue management between the software driver and the controller.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet INTERRUPT 'NOT EMPTY' STATUS REGISTER RCV INT TWO OPTIONS PACKET NUMBER RX FIFO PACKET NUMBER REGISTER TX EMPTY INT TX INT ALLOC INT RX FIFO TX FIFO 'EMPTY' RX PACKET NUMBER TX COMPLETION FIFO 'NOT EMPTY' TX DONE PACKET NUMBER CSMA ADDRESS CPU ADDRESS CSMA/CD LOGICAL ADDRESS PACKET # MMU M.S. BIT ONLY PACK # OUT PHYSICAL ADDRESS RAM Figure 10.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 11 Board Setup Information The following parameters are obtained from the EEPROM as board setup information: ETHERNET INDIVIDUAL ADDRESS I/O BASE ADDRESS MII INTERFACE All the above mentioned values are read from the EEPROM upon hardware reset.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet RELOAD and STORE are set by the user to initiate read and write operations respectively. Polling the value until read low is used to determine completion. When an EEPROM access is in progress the STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the LAN91C111 can be read or written until the EEPROM operation completes and both bits are clear. This mechanism is also valid for reset initiated reloads.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 16 BITS IOS2-0 WORD ADDRESS 000 0h CONFIGURATION REG. 1h BASE REG. 4h CONFIGURATION REG. 5h BASE REG. 8h CONFIGURATION REG. 9h BASE REG. Ch CONFIGURATION REG. Dh BASE REG. 10h CONFIGURATION REG. 11h BASE REG. 14h CONFIGURATION REG. 15h BASE REG. 18h CONFIGURATION REG. 19h BASE REG. 20h IA0-1 21h IA2-3 22h IA4-5 001 010 011 100 101 110 XXX Figure 11.1 64 X 16 Serial EEPROM Map Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 12 Application Considerations The LAN91C111 is envisioned to fit a few different bus types. This section describes the basic guidelines, system level implications and sample configurations for the most relevant bus types. All applications are based on buffered architectures with a private SRAM bus. FAST ETHERNET SLAVE ADAPTER Slave non-intelligent board implementing 100 Mbps and 10 Mbps speeds. Adapter requires: 1. LAN91C111 chip 2.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 12.1 VL Local Bus Signal Connections (continued) VL BUS SIGNAL LAN91C111 SIGNAL NOTES IRQn INTR0 Typically uses the interrupt lines on the ISA edge connector of VL bus D0-D31 D0-D31 32 bit data bus.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet VLBUS W/nR W/nR A2-A15 A2-A15 LCLK LCLK M/nIO AEN nRESET RESET IRQn LAN91C111 INTR0 D0-D31 D0-D31 nRDYRTN nRDYRTN nBE0-nBE3 nBE0-nBE3 nADS nADS Delay 1 LCLK nCYCLE nSRDY nLRDY nLDEV O.C. simulated O.C. nLDEV Figure 12.1 LAN91C111 on VL BUS HIGH-END ISA OR NON-BURST EISA MACHINES On ISA machines, the LAN91C111 is accessed as a 16 bit peripheral. The signal connections are listed in the following table: Table 12.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 12.2 High-End ISA or Non-Burst EISA Machines Signal Connectors (continued) ISA BUS SIGNAL LAN91C111 SIGNAL NOTES nIOWR nWR I/O Write strobe - asynchronous write access. Address is valid before leading edge. Data is latched on trailing edge. IOCHRDY ARDY This signal is negated on leading nRD, nWR if necessary. It is then asserted on CLK rising edge after the access condition is satisfied.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet ISA BUS A1-A15, AEN A1-A15, AEN RESET RESET nBE2, nBE3 VCC D0-D15 D0-D15 LAN91C111 INTR0 IRQ nIORD nRD nIOWR nWR A0 nBE0 nBE1 nSBHE nLDEV nIOCS16 O.C. Figure 12.2 LAN91C111 on ISA BUS EISA 32 BIT SLAVE On EISA the LAN91C111 is accessed as a 32 bit I/O slave, along with a Slave DMA type "C" data path option. As an I/O slave, the LAN91C111 uses asynchronous accesses.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 12.3 EISA 32 Bit Slave Signal Connections (continued) EISA BUS SIGNAL LAN91C111 SIGNAL Latched W-R combined with nCMD nRD I/O Read strobe - asynchronous read accesses. Address is valid before its leading edge. Must not be active during DMA bursts if DMA is supported. Latched W-R combined with nCMD nWR I/O Write strobe - asynchronous write access. Address is valid before leading edge . Data latched on trailing edge.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 12.3 EISA 32 Bit Slave Signal Connections (continued) EISA BUS SIGNAL LAN91C111 SIGNAL VCC nVLBUS GND A1 NOTES EISA BUS LA2- LA15 A2-A15 RESET RESET AEN AEN M/nIO D0-D31 D0-D31 INTR0 IRQn LAN91C111 nBE[0:3] nCMD nWR nBE[0:3] nRD LATCH + gates nWR LCLK BCLK nSTART nADS nLDEV nEX32 O.C. Figure 12.3 LAN91C111 on EISA BUS SMSC LAN91C111 REV C 109 DATASHEET Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 13 Operational Description 13.1 Maximum Guaranteed Ratings* Operating Temperature Range 0°C to +70°C for LAN91C111 (-40°C to 85°C for LAN91C111I) Storage Temperature Range -55C° to + 150°C Lead Temperature Range (soldering, 10 seconds) +325°C Positive Voltage on any pin, with respect to Ground VCC + 0.3V Negative Voltage on any pin, with respect to Ground -0.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PARAMETER Input Leakage (All I and IS buffers except pins with pullups/pulldowns) Low Input Leakage High Input Leakage SYMBOL MIN IIL TYP MAX UNITS COMMENTS -10 +10 µA VIN = 0 IIH -10 +10 µA VIN = VCC IIL -110 μA VIN = 0 +110 μA VIN = VCC 0.4 V IOL = 6 mA V IOH = -4 mA +10 µA VIN = 0 to VCC 0.4 V IOL = 6 mA V IOH = -4 mA +10 µA VIN = 0 to VCC 0.4 V IOL = 20 mA V IOH = -10 mA +10 µA VIN = 0 to VCC 0.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS 0.4 V IOL = 35 mA V IOH = -15 mA +10 µA VIN = 0 to VCC 0.4 V IOL = 4 mA V na +10 µA VIN = 0 to VCC Dynamic Current (Assuming internal PHY is used) I/O24 Type Buffer Low Output Level VOL High Output Level VOH 2.4 Output Leakage IOL -10 I/OD Type Buffer Low Output Level VOL High Output Level VOH 2.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 13.3 Twisted Pair Characteristics, Transmit VDD = 3.3v +/- 5% RBIAS = 11K +/- 1 %, no load LIMIT SYM Tov PARAMETER TP Differential Output Voltage UNIT CONDITIONS 1.050 Vpk 100 Mbps, UTP Mode, 100 Ohm Load 1.225 1.285 Vpk 100 Mbps, STP Mode, 150 Ohm Load 2.2 2.5 2.8 Vpk 10 Mbps, UTP Mode, 100 Ohm Load 2.694 3.062 3.429 Vpk 10 Mbps, STP Mode, 150 Ohm Load MIN TYP MAX 0.950 1.000 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet LIMIT SYM PARAMETER UNIT MIN TOIR TP Output Current Adjustment Range TYP 0.80 1.2 VDD = 3.3V, Adjustable with RBIAS, relative to TOIA with RBIAS=11K 0.86 1.16 VDD = 3.3V, Adjustable with LVL[3:0] Relative to Value at TLVL[3:0]=1000 TORA TP Output Current TLVL Step Accuracy TOR TP Output Resistance 10K Ohm TOC TP Output Capacitance 15 pF 13.4 CONDITIONS MAX +/-50 % Relative to Ideal Values in Table 3.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 14 Timing Diagrams t2 Address, AEN, nBE[3:0] Valid nADS t3 t4 Read Data Valid t6 t1 t5 nRD, nWR t5A Write Data Valid Figure 14.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 0ns 50ns 100ns Asynchronous Cycle -- Using nADS 150ns 200ns 250 t9 Addr,AEN,nBE[1:0] valid t8 nADS t3 t4 Read Data valid t6 t1 t5 nRD,nWR t5A Write Data valid Figure 14.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 0ns 50ns 100ns 150ns 200ns Asynchronous Cycle - nADS=0 250n t2 nDATACS t3A t4 Read Data valid t6A t1A t5 nRD,nWR t5A Write Data D0~D31 valid Figure 14.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PARAMETER MIN t26 ARDY Low Pulse Width 100 t26A Control Active to ARDY Low t13 Valid Data to ARDY High t17 t12 t22 TYP MAX UNITS 150 ns 10 ns 10 t18 ns t14 t18 Clock t12A nDATACS t17A W/nR t22A nCYCLE t20 Write Data a t20 t20 b c t15 nRDYRTN Figure 14.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PARAMETER MIN t22 nCYCLE Setup to LCLK Rising 5 ns t22A nCYCLE Hold After LCLK Rising 10 ns t17 t12 TYP MAX UNITS t14 Clock t12A nDATACS t17A W/nR nCYCLE t19 Read Data t19 a b c t15 nRDYRTN Figure 14.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet t8 nADS t9 Address, AEN, nBE[3:0] Valid t25 nLDEV Figure 14.7 Address Latching for All Modes PARAMETER MIN TYP MAX t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising 8 ns t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising 5 ns t25 A4-A15, AEN to nLDEV Delay 30 UNITS ns t18 t10 t20 Clock t9 Address, AEN, nBE[3:0] Valid t8 nADS t17A t16 W/nR t11 nCYCLE Write Data Valid t21 t21 nSRDY Figure 14.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PARAMETER MIN TYP MAX t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising 8 ns t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising 5 ns t10 nCYCLE Setup to LCLK Rising 5 ns t11 nCYCLE Hold after LCLK Rising (Non-Burst Mode) 3 ns t16 W/nR Setup to nCYCLE Active 0 ns t17A W/nR Hold after LCLK Rising with nSRDY Active 3 ns t18 Data Setup to LCLK Rising (Write) 15 ns t20 Data Hold from LCLK Rising (Write) 4 ns t21 nSRDY Delay fr
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PARAMETER MIN TYP MAX t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising 8 ns t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising 5 ns t10 nCYCLE Setup to LCLK Rising 5 ns t11 nCYCLE Hold after LCLK Rising (Non-Burst Mode) 3 ns t16 W/nR Setup to nCYCLE Active 0 ns t20 Data Hold from LCLK Rising (Read) 4 ns t21 nSRDY Delay from LCLK Rising t23 nRDYRTN Setup to LCLK Rising 3 ns t24 nRDYRTN Hold after LCLK Rising 3 ns 7 UNIT
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet AC TEST TIMING CONDITIONS Unless otherwise noted, all test conditions are as follows: 1. VDD = 3.3V +/-5% 2. RBIAS = 11K +/- 1%, no load 3. Measurement Points: 4. TPO±, TPI±: 0.0 V During Data, ±0.3V at start/end of packet 5. All other inputs and outputs: 1.4 Volts Table 14.1 Transmit Timing Characteristics LIMIT SYM PARAMETER MIN t30 Transmit Propagation Delay t31 TYP UNIT CONDITIONS 140 nS 100Mbps 600 nS 10Mbps ±0.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 14.2 Receive Timing Characteristics LIMIT SYM PARAMETER MIN t36 t37 TYP Receive Input Jitter SOI Pulse Minimum Width Required for Idle Detection UNIT CONDITIONS ±3.0 nS pk-pk 100Mbps ±13.5 nS pk-pk 10Mbps 200 nS 10Mbps Measure TPI± from last zero cross to 0.3V point MAX 125 t 36 TPI± DATA DATA DATA DATA DATA SOI t 37 Figure 14.12 Receive Timing, End of Packet - 10 MBPS Table 14.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet MII 100 Mbps TPO± I DATA DATA DATA DATA DATA DATA DATA DATA DATA TPI± I I I I J K DATA DATA DATA DATA t DATA T DATA DATA DATA R I I 38 Collision Observed by Physical Layer t 34 t 35 LEDn MII 10 Mbps TPO± TPI± t 38 Collision Observed by Physical Layer t 34 t 35 LEDn Figure 14.13 Collision Timing, Receive SMSC LAN91C111 REV C 125 DATASHEET Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet MII 100 Mbps TPI± I TPO± I DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA I I I J K t DATA DATA DATA DATA T R I I 39 Collision Observed by Physical Layer t 34 t 35 LEDn MII 10 Mbps TPI± TPO± t 39 Collision Observed by Physical Layer t 34 t 35 LEDn Figure 14.14 Collision Timing, Transmit Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet MII 100 Mbps TPO± I I J K t TPO± I I I DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA 40 I I J K JAM JAM JAM JAM T R I I I t 41 Collision Observed by Physical Layer MII 10 Mbps TPI± t TPO± 40 JAM JAM JAM JAM Figure 14.15 Jam Timing SMSC LAN91C111 REV C 127 DATASHEET Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 14.4 Link Pulse Timing Characteristics LIMIT SYM UNIT CONDITIONS PARAMETER MIN TYP MAX t42 NLP Transmit Link Pulse Width See Figure 7.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet TPO± t 42 t 43 a.) Transmit NLP TPI± t 44 t 45 t 46 t 47 LEDn b.) Receive NLP Figure 14.16 Link Pulse Timing SMSC LAN91C111 REV C 129 DATASHEET Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet CLK DATA CLK DATA CLK CLK DATA TPO± t 48 t 49 t 50 t 51 a.) Transmit FLP and Transmit FLP Burst CLK DATA CLK DATA TPI± 31.25 t 52 62.5 93.75 125 156.25 t 53 t 54 t 55 t 56 b.) Receive FLP TPI± t 59 t 57 t 58 LEDn c.) Receive FLP Burst Figure 14.17 FLP Link Pulse Timing Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 15 Package Outlines Figure 15.1 128 Pin TQFP Package Outline, 14X14X1.0 Body Table 15.1 128 Pin TQFP Package Parameters A A1 A2 D D/2 D1 E E/2 E1 H L L1 e q W R1 R2 ccc ccc MIN NOMINAL MAX REMARK ~ 0.05 0.95 15.80 7.90 13.80 15.80 7.90 13.80 0.09 0.45 ~ 0.40 Basic 0o 0.13 0.08 0.08 ~ ~ ~ ~ 1.00 16.00 8.00 14.00 16.00 8.00 14.00 ~ 0.60 1.00 1.20 0.15 1.05 16.20 8.10 14.20 16.20 8.10 14.20 0.20 0.75 ~ ~ 0.18 ~ ~ ~ ~ 7o 0.23 ~ 0.20 0.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Figure 15.2 128 Pin QFP Package Outline, 3.9 MM Footprint Table 15.2 128 Pin QFP Package Parameters A A1 A2 D D/2 D1 E E/2 E1 H L L1 e q W R1 R2 ccc ccc MIN NOMINAL MAX REMARKS ~ 0.05 2.55 23.70 11.85 19.90 17.70 8.85 13.90 ~ 0.73 ~ 0.5 Basic 0o 0.10 0.13 0.13 ~ ~ ~ ~ ~ 23.90 11.95 20.0 17.90 8.95 14.00 ~ 0.88 1.95 3.4 0.5 3.05 24.10 12.05 20.10 18.10 9.05 14.10 ~ 1.03 ~ ~ ~ ~ ~ ~ ~ 7o 0.30 ~ 0.30 0.0762 0.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 16 Datasheet Revision History Table 16.1 Customer Revision History REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION Rev. 1.92 (06-27-11) Section 7.7.17, "PHY Powerdown," on page 41 Added note stating that the PDN bit must not be set when the device is in external PHY mode. Rev. 1.92 (04-27-11) Table 10.