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SMSC LAN9220 DATASHEET Revision 2.9 (03-01-12)

Datasheet

PRODUCT FEATURES

LAN9220

16-bit Non-PCI Small Form Factor

10/100 Ethernet Controller with

Variable Voltage I/O & HP Auto-MDIX

Support

Highlights

 Efficient architecture with low CPU overhead

 Easily interfaces to most 16-bit embedded CPU’s

 1.8V to 3.3V variable voltage I/O accommodates wide

range of I/O signalling without voltage level shifters

 Integrated PHY with HP Auto-MDIX support

 Integrated checksum offload engine helps reduce

CPU load

 Low pin count and small body size package for small

form factor system designs

Target Applications

 Cable, satellite, and IP set-top boxes

 Digital video recorders

 Video-over IP solutions, IP PBX & video phones

 Wireless routers & access points

 Audio distribution systems

 Printers, kiosks, security systems

 General embedded applications

Key Benefits

 Non-PCI Ethernet controller for standard performance

applications

— 16-bit interface

— Burst-mode read support

 Minimizes dropped packets

— Internal buffer memory can store over 200 packets

— Automatic PAUSE and back-pressure flow control

 Minimizes CPU overhead

— Supports Slave-DMA

— Interrupt Pin with Programmable Hold-off timer

 Reduces system cost and increases design flexibility

 SRAM-like interface easily interfaces to most

embedded CPU’s or SoC’s

 Reduced Power Modes

— Numerous power management modes

— Wake on LAN

— Magic packet wakeup

— Wakeup indicator event signal

— Link Status Change

 Single chip Ethernet controller

— Fully compliant with IEEE 802.3/802.3u standards

— Integrated Ethernet MAC and PHY

— 10BASE-T and 100BASE-TX support

— Full- and Half-duplex support

— Full-duplex flow control

— Backpressure for half-duplex flow control

— Preamble generation and removal

— Automatic 32-bit CRC generation and checking

— Automatic payload padding and pad removal

— Loop-back modes

 Flexible address filtering modes

— One 48-bit perfect address

— 64 hash-filtered multicast addresses

— Pass all multicast

— Promiscuous mode

— Inverse filtering

— Pass all incoming with status report

— Disable reception of broadcast packets

 Integrated 10/100 Ethernet PHY

— Supports HP Auto-MDIX

— Auto-negotiation

— Supports energy-detect power down

 Host bus interface

— Simple, SRAM-like interface

— 16-bit data bus

— 16Kbyte FIFO with flexible TX/RX allocation

— One configurable host interrupt

 Miscellaneous features

— Small form factor, 56-pin QFN lead-free RoHS

Compliant package

— Integrated 1.8V regulator

— Integrated checksum offload engine

— Mixed endian support

— General Purpose Timer

— Optional EEPROM interface

— Support for 3 status LEDs multiplexed with

Programmable GPIO signals

 Single 3.3V Power Supply with Variable Voltage I/O

 0°C to +70°C Commercial Temperature Support

Summary of content (151 pages)

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LAN9220 16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support PRODUCT FEATURES Datasheet Highlights Efficient architecture with low CPU overhead Easily interfaces to most 16-bit embedded CPU’s 1.8V to 3.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Order Number(s): LAN9220-ABZJ for 56-pin, QFN Lead-free RoHS Compliant package (0 to +70°C Temp Range) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit www.smsc.com/rohs Copyright © 2012 SMSC or its subsidiaries. All rights reserved.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table of Contents Chapter 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Block Overview . . . . . . . . . . . . . . . .
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 3.12 3.13 TX Data Path Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.1 TX Buffer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.2 TX Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.4 5.5 5.3.3 INT_STS—Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.4 INT_EN—Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.5 BYTE_TEST—Byte Order Test Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.3.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.2.1 Special Restrictions on Back-to-Back Write/Read Cycles . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Special Restrictions on Back-to-Back Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet List of Figures Figure 1.1 Figure 1.2 Figure 2.1 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 Figure 3.7 Figure 3.8 Figure 3.9 Figure 3.10 Figure 3.11 Figure 3.12 Figure 3.13 Figure 3.14 Figure 3.15 Figure 3.16 Figure 3.17 Figure 3.18 Figure 3.19 Figure 3.20 Figure 3.21 Figure 3.22 Figure 3.23 Figure 3.24 Figure 3.25 Figure 3.26 Figure 3.27 Figure 4.1 Figure 4.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet List of Tables Table 2.1 Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2.2 LAN Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2.3 Serial EEPROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . .
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 7.10 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.11 LAN9220 Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.1 56 Pin QFN Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Chapter 1 General Description The LAN9220 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9220 is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, and supports HP Auto-MDIX.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 1.1 Block Diagram System Memory System Peripherals Microprocessor/ Microcontroller Magnetics System Bus Ethernet LAN9220 LEDS/ GPIO 25MHz XTAL EEPROM (Optional) Figure 1.1 System Block Diagram The SMSC LAN9220 integrated 10/100 MAC/PHY controller is a peripheral chip that performs the function of translating parallel data from a host controller into Ethernet packets.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 1.2 Internal Block Overview This section provides an overview of each of these functional blocks as shown in Figure 1.2, "Internal Block Diagram". 25MHz EEPROM (Optional) +3.3V PME Wakup Indicator Power Management Host Bus Interface (HBI) 16-bit SRAM I/F 3.3V to 1.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet can control or access the TX or RX data. The MAC buffers (both TX and RX) are in effect the working buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first to the RX FIFOs for the host to access the data. For TX operations, the MIL operates in store-and-forward mode and will queue an entire frame before beginning transmission. 1.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 1.11 Host Bus Interface (SRAM Interface) The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as an interface for the LAN9220 Control and Status Registers (CSR’s). The host bus interface is the primary bus for connection to the embedded host system. This interface models an asynchronous SRAM.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet nRESET PME EECLK/GPO4** EECS EEDIO/GPO3** VDD18CORE D0 D1 D2 D3 D4 D5 VDDVARIO D6 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Chapter 2 Pin Description and Configuration IRQ 43 28 D7 TPO- 44 27 D8 TPO+ 45 26 D9 VDD33A 46 25 D10 TPI- 47 56-QFN 24 VDDVARIO TPI+ 48 (TOP VIEW) 23 D11 VDD33A 49 22 D12 SMSC LAN9220 VSS 14 nRD TEST 15
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-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 2.1 Pin List Table 2.1 Host Bus Interface Signals NAME SYMBOL BUFFER TYPE # PINS Host Data D[15:0] VIS/VO8 16 Bi-directional data port. Host Address A[7:1] VIS 7 7-bit Address Port. Used to select Internal CSR’s and TX and RX FIFOs. Read Strobe nRD VIS 1 Active low strobe to indicate a read cycle. Write Strobe nWR VIS 1 Active low strobe to indicate a write cycle.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 2.3 Serial EEPROM Interface Signals NAME SYMBOL EEPROM Data, GPO3, TX_EN, TX_CLK EEDIO/GPO3/ TX_EN/TX_CLK BUFFER TYPE NUM PINS VIS/VO8 1 DESCRIPTION EEPROM Data: This bi-directional pin can be connected to a serial EEPROM DIO. This is optional.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 2.4 System and Power Signals NAME SYMBOL BUFFER TYPE NUM PINS Crystal 1, Clock In XTAL1/CLKIN lCLK 1 External 25MHz Crystal Input. This pin can also be connected to single-ended TTL oscillator (CLKIN). If this method is implemented, XTAL2 should be left unconnected. Crystal 2 XTAL2 OCLK 1 External 25MHz Crystal output.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 2.4 System and Power Signals (continued) NAME SYMBOL Test TEST General Purpose I/O data, nLED1 (Speed Indicator), nLED2 (Link & Activity Indicator), GPIO[2:0]/ nLED[3:1] BUFFER TYPE NUM PINS VIS (PD) 1 VIS/ VO12/ VOD12 3 DESCRIPTION Reserved for internal test purposes only. Note: nLED3 (FullDuplex Indicator). When operating at a reduced VDDVARIO voltage (less than 3.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 2.4 System and Power Signals (continued) NAME SYMBOL BUFFER TYPE NUM PINS Core Voltage Decoupling VDD18CORE P 2 DESCRIPTION +1.8 V from internal core regulator. Both pins must be connected together externally. Each pin requires a 0.01uF decoupling capacitor. In addition, pin 2 requires a bulk 4.7uF capacitor (<2 Ohm ESR) in parallel.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 2.2 External Pull-Up/Pull-Down Resistors As detailed in Table 2.6, when using an external pull-up or pull-down resistor, the required value is dependant on the operating voltage. Usage of recommended pull-up/pull-down resistor values is required to ensure proper operation. Table 2.6 External Pull-Up/Pull-Down Resistor Values 2.3 I/O VOLTAGE PULL-UP/PULL-DOWN RESISTOR VALUE (OHMS) 3.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Chapter 3 Functional Description 3.1 10/100 Ethernet MAC The Ethernet Media Access controller (MAC) incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.3-compliant node and provides an interface between the host subsystem and the internal Ethernet PHY. The MAC can operate in either 100-Mbps or 10-Mbps mode.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet The LAN9220 can store up to 250 Ethernet packets utilizing FIFOs, totaling 16K bytes, with a packet granularity of 4 bytes. This memory is shared by the RX and TX blocks and is configurable in terms of allocation. This depth of buffer storage minimizes or eliminates receive overruns. 3.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Figure 3.1 VLAN Frame 3.3 Address Filtering Functional Description The Ethernet address fields of an Ethernet Packet, consists of two 6-byte fields: one for the destination address and one for the source address. The first bit of the destination address signifies whether it is a physical address or a multicast address.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 3.1 Address Filtering Modes (continued) MCPAS PRMS INVFILT HO HPFILT 0 0 0 1 1 Hash Filtering for physical and multicast addresses 0 0 1 0 0 Inverse Filtering X 1 0 X X Promiscuous 1 0 0 0 X Pass all multicast frames. Frames with physical addresses are perfect-filtered 1 0 0 1 1 Pass all multicast frames.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 3.5 Wake-up Frame Detection Setting the Wake-Up Frame Enable bit (WUEN) in the “WUCSR—Wake-up Control and Status Register”, places the LAN9220 MAC in the wake-up frame detection mode. In this mode, normal data reception is disabled, and detection logic within the MAC examines receive data for the preprogrammed wake-up frame patterns.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 3.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 3.5 Filter i Offset Bit Definitions FILTER I OFFSET DESCRIPTION FIELD 7:0 DESCRIPTION Pattern Offset: The offset of the first byte in the frame on which CRC is checked for wake-up frame recognition. The minimum value of this field must be 12 since there should be no CRC check for the destination address and the source address fields.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Destination Address Source Address ……………FF FF FF FF FF FF 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 …CRC It should be noted that Magic Packet det
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Example frame configurations: DST 0 SRC p r o t 2 3 1 L3 Packet F C S Calculate Checksum 1DWORD Figure 3.3 Type II Ethernet Frame DST 0 SRC 1 2 8 t V 1 y I 0 p D 0 e 3 L3 Packet F C S 4 Calculate Checksum 1DWORD Figure 3.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet {DSAP, SSAP, CTRL, OUI[23:16]} DST 0 S 8 V L N 1 I e A 0 Dn P 0 0 SRC 1 2 3 4 {OUI[15:0], PID[15:0]} S N A P 1 5 L3 Packet F C S 6 Calculate Checksum 1DWORD Figure 3.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 3.6.1.1 RX Checksum Calculation The checksum is calculated 16 bits at a time. In the case of an odd sized frame, an extra byte of zero is used to pad up to 16 bits. Consider the following packet: DA, SA, Type, B0, B1, B2 … BN, FCS Let [A, B] = A*256 + B; If the packet has an even number of octets then checksum = [B1, B0] + C0 + [B3, B2] + C1 + … + [BN, BN-1] + CN-1 Where C0, C1, ...
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 3.7 TX Checksum Preamble FIELD DESCRIPTION 31:28 RESERVED 27:16 TXCSLOC - TX Checksum Location This field specifies the byte offset where the TX checksum will be inserted in the TX packet. The checksum will replace two bytes of data starting at this offset.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 3.7.2 Bus Reads The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot change during a sixteen bit read). No ordering requirements exist.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet C SR s and Status FIFO s FPO R TEN D (H W _C FG [29]) W O R D _SW A P R X/TX D ata FIFO Port A ccess (addresses 00h to 3C h) R X/TX D ata FIFO D irect A ccess (FIFO _SEL = 1) FIFO Port Endian O rdering Logic D irect FIFO A ccess Endian O rdering Logic FSELEN D (H W _C FG [28]) "W O R D SW A P" Logic D [15:0] (H ost D ata B us) Figure 3.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet WORD_SWAP != FFFF_FFFFh BIG ENDIAN LITTLE ENDIAN (FPORTEND = 1 for Data FIFO port access on addresses 00h-3Ch) AND/OR (FSELEND = 1 for Data FIFO direct access when FIFO_SEL=1) (FPORTEND = 0 for Data FIFO port access on addresses 00h-3Ch) AND/OR (FSELEND = 0 for Data FIFO direct access when FIFO_SEL=1) INTERNAL FIFO ORDER INTERNAL FIFO ORDER MSB 31 MSB LSB 24 23 3 16 15 8 2
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet WORD_SWAP = FFFF_FFFFh WORD_SWAP != FFFF_FFFFh Table 3.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 3.9 EEPROM Interface The LAN9220 can optionally load its MAC address from an external serial EEPROM. If a properly configured EEPROM is detected by the LAN9220 at power-up, hard reset or soft reset, the ADDRH and ADDRL registers will be loaded with the contents of the EEPROM.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet If an operation is attempted, and an EEPROM device does not respond within 30mS, the LAN9220 will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be set. Figure 3.10, "EEPROM Access Flow Diagram" illustrates the host accesses required to perform an EEPROM Read or Write operation.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet ERASE (Erase Location): If erase/write operations are enabled in the EEPROM, this command will erase the location selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the EEPROM does not respond within 30ms. tCSL EECS EECLK EEDIO (OUTPUT) 1 1 1 A6 A0 EEDIO (INPUT) Figure 3.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet EWDS (Erase/Write Disable): After issued, the EEPROM will ignore erase and write commands. To re-enable erase/write operations issue the EWEN command. tCSL EECS EECLK EEDIO (OUTPUT) 1 0 0 0 0 EEDIO (INPUT) Figure 3.13 EEPROM EWDS Cycle EWEN (Erase/Write Enable): Enables the EEPROM for erase and write operations.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet READ (Read Location): This command will cause a read of the EEPROM location pointed to by EPC Address (EPC_ADDR). The result of the read is available in the E2P_DATA register. tCSL EECS EECLK EEDIO (OUTPUT) 1 1 0 A6 A0 EEDIO (INPUT) D7 D0 Figure 3.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 3.9, "Required EECLK Cycles", shown below, shows the number of EECLK cycles required for each EEPROM operation. Table 3.9 Required EECLK Cycles 3.9.2.2 OPERATION REQUIRED EECLK CYCLES ERASE 10 ERAL 10 EWDS 10 EWEN 10 READ 18 WRITE 18 WRAL 18 MAC Address Reload The MAC address can be reloaded from the EEPROM via a host command to the E2P_CMD register.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Note 3.4 The LAN9220 must always be read at least once after power-up, reset, or upon return from a power-saving state, otherwise write operations will not function. In system configurations where the PME signal is shared amongst multiple devices, the WUPS field within the PMT_CTRL register can be read to determine which LAN9220 device is driving the PME signal.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Note 3.10 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the setting of PME_EN. A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the LAN9220 to the D0 state and will reset the PM_MODE field to the D0 state.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 3.10.2.3 Power Management Event Indicators Figure 3.18 is a simplified block diagram of the logic that controls the external PME, and internal pme_interrupt signals. The pme_interrupt signal is used to set the PME_INT status bit in the INT_STS register, which, if enabled, will generate a host interrupt upon detection of a power management event.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 3.10.3.2 Energy Detect Power-Down This power-down mode is activated by setting the Phy register bit 17.13 to 1. Please refer to Section 5.5.8, "Mode Control/Status," on page 122 for additional information on this register.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) after an internal reset (22ms). If the software driver polls this bit and it is not set within 100ms, then an error condition occurred. 3.11.1 Hardware Reset Input (nRESET) A hardware reset will occur when the nRESET input signal is driven low.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet ‘A’ and TX command ‘B’). The TX command instructs the LAN9220 on the handling of the associated buffer. Packet boundaries are delineated using control bits within the TX command. The host provides a 16-bit Packet Tag field in the TX command. The Packet Tag value is appended to the corresponding TX status DWORD.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet init Idle TX Status Available Check available FIFO space Read TX Status (optional) Write TX Command Write Start Padding (optional) Last Buffer in Packet Not Last Buffer Write Buffer Figure 3.19 Simplified Host TX Flow Diagram 3.12.1 TX Buffer Format TX buffers exist in the host’s memory in a given format.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Host Write 31 Order 0 1st TX Command 'A' 2nd TX Command 'B' 3rd Optional offset DWORD0 . . . Optional offset DWORDn Offset + Data DWORD0 . . . . . Last Data & PAD Optional Pad DWORD0 . . . Optional Pad DWORDn Last Figure 3.20 TX Buffer Format Figure 3.20, "TX Buffer Format", shows the TX Buffer as it is written into the LAN9220.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet TX COMMAND ‘A’ Table 3.12 TX Command 'A' Format BITS DESCRIPTION 31 Interrupt on Completion. When set, the TXDONE flag will be asserted when the current buffer has been fully loaded into the TX FIFO. This flag may be optionally mapped to a host interrupt. 30:26 Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet TX COMMAND ‘B’ Table 3.13 TX Command 'B' Format BITS DESCRIPTION 31:16 Packet Tag. The host should write a unique packet identifier to this field. This identifier is added to the corresponding TX status word and can be used by the host to correlate TX status words with their corresponding packets. Note: The use of packet tags is not required by the hardware.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Middle buffers (i.e., those with First Segment = Last Segment = 0) must be greater than, or equal to 4 bytes in length The final buffer of any transmit packet can be any length The MIL operates in store-and-forward mode and has specific rules with respect to fragmented packets.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet BITS 10 DESCRIPTION No Carrier. When set, this bit indicates that the carrier signal from the transceiver was not present during transmission. Note: During 10/100 Mbps full-duplex transmission, the value of this bit is invalid and should be ignored. 9 Late Collision. When set, indicates that the packet transmission was aborted after the collision window of 64 bytes.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 3.12.6 Transmit Examples 3.12.6.1 TX Example 1 In this example a single, 111-Byte Ethernet packet will be transmitted. This packet is divided into three buffers.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Figure 3.21, "TX Example 1" illustrates the TX command structure for this example, and also shows how data is passed to the TX data FIFO.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 3.12.6.2 TX Example 2 In this example, a single 183-Byte Ethernet packet will be transmitted. This packet is in a single buffer as follows: 2-Byte “Data Start Offset” 183-Bytes of payload data 4-Byte “Buffer End Alignment” Figure 3.22, "TX Example 2" illustrates the TX command structure for this example, and also shows how data is passed to the TX data FIFO.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 3.12.6.3 TX Example 3 In this example a single, 111-Byte Ethernet packet will be transmitted with a TX checksum. This packet is divided into four buffers.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Data Written to the Ethernet Controller TX Command 'A' Buffer End Alignment = 1 Data Start Offset = 4 First Segment = 1 Last Segment = 0 Buffer Size = 4 31 NOTE: When enabled, the TX Checksum Preamble is pre-pended to data to be transmitted.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 3.12.7 Transmitter Errors If the Transmitter Error (TXE) flag is asserted for any reason, the transmitter will continue operation. TX Error (TXE) will be asserted under the following conditions: 3.12.8 If the actual packet length count does not match the Packet Length field as defined in the TX command.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 3.13.1 RX Slave PIO Operation Using PIO mode, the host can either implement a polling or interrupt scheme to empty the received packet out of the RX data FIFO. The host will remain in the idle state until it receives an indication (interrupt or polling) that data is available in the RX data FIFO.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 3.13.1.1 Receive Data FIFO Fast Forward The RX data path implements an automatic data discard function. Using the RX data FIFO Fast Forward bit (RX_FFWD) in the RX_DP_CTRL register, the host can instruct the LAN9220 to skip the packet at the head of the RX data FIFO. The RX data FIFO pointers are automatically incremented to the beginning of the next RX packet.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 3.13.2 RX Packet Format The RX status words can be read from the RX status FIFO port, while the RX data packets can be read from the RX data FIFO. RX data packets are formatted in a specific manner before the host can read them as shown in Figure 3.26.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Host Read Order 31 0 1st Optional offset DWORD0 2nd . . Optional offset DWORDn ofs + First Data DWORD . . . . Last Data DWORD RX Checksum Optional Pad DWORD0 . . Last Optional Pad DWORDn Figure 3.27 RX Packet Format with RX Checksum 3.13.3 RX Status Format BITS DESCRIPTION 31 Reserved. This bit is reserved. Reads 0. 30 Filtering Fail.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet BITS DESCRIPTION 7 Frame Too Long. When set, this bit indicates that the frame length exceeds the maximum Ethernet specification of 1518 bytes. This is only a frame too long indication and will not cause the frame reception to be truncated. 6 Collision Seen. When set, this bit indicates that the frame has seen a collision after the collision window.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Chapter 4 Internal Ethernet PHY 4.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 4.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 4.1 4B/5B Code Table (continued) CODE GROUP SYM 00101 V INVALID, RX_ER if during RX_DV INVALID 01000 V INVALID, RX_ER if during RX_DV INVALID 01100 V INVALID, RX_ER if during RX_DV INVALID 10000 V INVALID, RX_ER if during RX_DV INVALID 4.2.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 100M PLL RX_CLK MAC Internal MII 25MHz by 4 bits 25MHz by 4 bits MII 4B/5B Decoder 25MHz by 5 bits Descrambler and SIPO 125 Mbps Serial NRZI Converter A/D Converter NRZI MLT-3 MLT-3 Converter Magnetics DSP: Timing recovery, Equalizer and BLW Correction MLT-3 RJ45 MLT-3 MLT-3 CAT-5 6 bit Data Figure 4.2 Receive Data Path 4.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 4.3.4 Descrambling The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel Out (SIPO) conversion of the data. During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the incoming stream.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet clock. This is used to Manchester encode the NRZ data stream. When no data is being transmitted (TX_EN is low), the TX10M block outputs Normal Link Pulses (NLPs) to maintain communications with the remote link partner. 4.4.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet performance mode of operation supported by both sides. Auto-negotiation is fully defined in clause 28 of the IEEE 802.3 specification. Once auto-negotiation has completed, information about the resolved link can be passed back to the controller via the internal Serial Management Interface (SMI).
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Once a capability match has been determined, the link code words are repeated with the acknowledge bit set. Any difference in the main content of the link code words at this time will cause auto-negotiation to re-start. Auto-negotiation will also re-start if not all of the required FLP bursts are received.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet full-duplex transmission. Therefore, these signals cannot be used as a verification method of transmitted packets when transmitting in 10/100 Mbps full-duplex modes. Table 4.2 CRS Behavior MODE SPEED DUPLEX ACTIVITY CRS BEHAVIOR (Note 4.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet The figure below shows the signal names at the RJ-45 connector, The mapping of these signals to the pins on the LAN9220 is as follows: TXP = TPO+ TXN = TPORXP = TPI+ RXN = TPI- Figure 4.3 Direct Cable Connection vs. Cross-over Cable Connection Revision 2.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Chapter 5 Register Description The following section describes all LAN9220 registers and data ports.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.1 Register Nomenclature and Access Attributes SYMBOL DESCRIPTION RO Read Only: If a register is read only, writes to this register have no effect. WO Write Only: If a register is write only, reads always return 0. R/W Read/Write: A register with this attribute can be read and written R/WC Read/Write Clear: A register bit with this attribute can be read and written.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3 System Control and Status Registers Table 5.1, "Direct Address Register Map", lists the registers that are directly addressable by the host bus. Table 5.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.1 ID_REV—Chip ID and Revision Offset: 50h Size: 32 bits This register contains the ID and Revision fields for this design. BITS DESCRIPTION TYPE DEFAULT 31-16 Chip ID. This read-only field identifies this design RO 9220h 15-0 Chip Revision RO 0000h 5.3.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet BITS DESCRIPTION TYPE DEFAULT 4 IRQ Polarity (IRQ_POL) – When cleared, enables the IRQ line to function as an active low output. When set, the IRQ output is active high. When IRQ is configured as an open-drain output this field is ignored, and the interrupt output is always active low.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.3 INT_STS—Interrupt Status Register Offset: 58h Size: 32 bits This register contains the current status of the generated interrupts. Writing a 1 to the corresponding bits acknowledges and clears the interrupt. BITS 31 30-26 DESCRIPTION Software Interrupt (SW_INT). This interrupt is generated when the SW_INT_EN bit is set high. Writing a one clears this interrupt.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet BITS 12:11 DESCRIPTION Reserved TYPE DEFAULT RO - 10 TX Data FIFO Overrun Interrupt (TDFO). Generated when the TX data FIFO is full, and another write is attempted. R/WC 0 9 TX Data FIFO Available Interrupt (TDFA). Generated when the TX data FIFO available space is greater than the programmed level. R/WC 0 8 TX Status FIFO Full Interrupt (TSFF).
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.4 INT_EN—Interrupt Enable Register Offset: 5Ch Size: 32 bits This register contains the interrupt masks for IRQ. Writing 1 to any of the bits enables the corresponding interrupt as a source for IRQ. Bits in the INT_STS register will still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt in this register.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.5 BYTE_TEST—Byte Order Test Register Offset: 64h Size: 32 bits This register can be used to determine the byte ordering of the current configuration BITS 31:0 DESCRIPTION Byte Test 5.3.6 TYPE DEFAULT RO 87654321h FIFO_INT—FIFO Level Interrupts Offset: 68h Size: 32 bits This register configures the limits where the FIFO Controllers will generate system interrupts.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.7 RX_CFG—Receive Configuration Register Offset: 6Ch Size: 32 bits This register controls the LAN9220 receive engine. BITS DESCRIPTION TYPE DEFAULT 31:30 RX End Alignment. This field specifies the alignment that must be maintained on the last data transfer of a buffer. The LAN9220 will add extra DWORDs of data up to the alignment specified in the table below.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.8 TX_CFG—Transmit Configuration Register Offset: 70h Size: 32 bits This register controls the transmit functions on the LAN9220 Ethernet Controller. BITS TYPE DEFAULT Reserved. RO - 15 Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX status FIFO of all pending status DWORD’s. When a ‘1’ is written, the TX status pointers are cleared to zero.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.9 HW_CFG—Hardware Configuration Register Offset: 74h Size: 32 bits Note: The transmitter and receiver must be stopped before writing to this register. Refer to Section 3.12.8, "Stopping and Starting the Transmitter," on page 61 and Section 3.13.4, "Stopping and Starting the Receiver," on page 66 for details on stopping the transmitter and receiver.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet BITS DESCRIPTION TYPE DEFAULT 0 Soft Reset (SRST). Writing 1 generates a software initiated reset. This reset generates a full reset of the MAC CSR’s. The SCSR’s (system command and status registers) are reset except for any NASR bits. Soft reset also clears any TX or RX errors (TXE/RXE). This bit is self-clearing.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.9.1 Allowable settings for Configurable FIFO Memory Allocation TX and RX FIFO space is configurable through the CSR - HW_CFG register defined above. The user must select the FIFO allocation by setting the TX FIFO Size (TX_FIF_SZ) field in the hardware configuration (HW_CFG) register.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet In addition to the host-accessible FIFOs, the MAC Interface Layer (MIL) contains an additional 2K bytes of TX, and 128 bytes of RX FIFO buffering. These sizes are fixed, and cannot be adjusted by the host. As space in the TX MIL (Mac Interface Layer) FIFO frees, data is moved into it from the TX data FIFO.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.11 RX_FIFO_INF—Receive FIFO Information Register Offset: 7Ch Size: 32 bits This register contains the used space in the receive FIFOs of the LAN9220 Ethernet Controller. BITS DESCRIPTION TYPE DEFAULT 31-24 Reserved RO - 23-16 RX Status FIFO Used Space (RXSUSED). Indicates the amount of space in DWORDs, used in the RX Status FIFO.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.13 PMT_CTRL— Power Management Control Register Offset: 84h Size: 32 bits This register controls the Power Management features. This register can be read while the LAN9220 is in a power saving mode. Note: The LAN9220 must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet BITS 5-4 DESCRIPTION WAKE-UP Status (WUPS) – This field indicates the cause of a wake-up event detection as follows TYPE DEFAULT R/WC 00 R/W 0b 00b -- No wake-up event detected 01b -- Energy detected 10b -- Wake-up frame or magic packet detected 11b -- Indicates multiple events occurred WUPS bits are cleared by writing a ‘1’ to the appropriate bit.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.14 GPIO_CFG—General Purpose IO Configuration Register Offset: 88h Size: 32 bits This register configures the GPIO and LED functions. BITS TYPE DEFAULT Reserved RO - LED[3:1] enable (LEDx_EN). A ‘1’ sets the associated pin as an LED output. When cleared low, the pin functions as a GPIO signal.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet BITS DESCRIPTION TYPE DEFAULT 4:3 GPO Data 3-4 (GPODn). The value written is reflected on GPOn. GPO3 – bit 3 GPO4 – bit 4 R/W 00 2:0 GPIO Data 0-2 (GPIODn). When enabled as an output, the value written is reflected on GPIOn. When read, GPIOn reflects the current state of the corresponding GPIO pin. GPIO0 – bit 0 GPIO1 – bit 1 GPIO2 – bit 2 R/W 000 Table 5.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.16 GPT_CNT-General Purpose Timer Current Count Register Offset: 90h Size: 32 bits This register reflects the current value of the GP Timer. BITS DESCRIPTION TYPE DEFAULT 31-16 Reserved RO - 15-0 General Purpose Timer Current Count (GPT_CNT). This 16-bit field reflects the current value of the GP Timer. RO FFFFh 5.3.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.18 FREE_RUN—Free-Run 25MHz Counter Offset: 9Ch Size: 32 bits This register reflects the value of the free-running 25MHz counter. BITS 31:0 5.3.19 DESCRIPTION TYPE DEFAULT RO - Free Running SCLK Counter (FR_CNT): Note: This field reflects the value of a free-running 32-bit counter. At reset the counter starts at zero and is incremented for every 25MHz cycle.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.20 MAC_CSR_CMD – MAC CSR Synchronizer Command Register Offset: A4h Size: 32 bits This register is used to control the read and write operations with the MAC CSR’s BITS DESCRIPTION TYPE DEFAULT 31 CSR Busy. When a 1 is written into this bit, the read or write operation is performed to the specified MAC CSR. This bit will remain set until the operation is complete.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.22 AFC_CFG – Automatic Flow Control Configuration Register Offset: ACh Size: 32 bits This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause frames and back pressure. Note: The LAN9220 will not transmit pause frames or assert back pressure if the transmitter is disabled.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet BITS DESCRIPTION TYPE DEFAULT 0 Flow Control on Any Frame (FCANY). When this bit is set, the LAN9220 will assert back pressure, or transmit a pause frame when the AFC level is reached and any frame is received. Setting this bit enables full-duplex flow control when the LAN9220 is operating in full-duplex mode.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.3.23 E2P_CMD – EEPROM Command Register Offset: B0h Size: 32 bits This register is used to control the read and write operations with the Serial EEPROM. BITS DESCRIPTION TYPE DEFAULT 31 EPC Busy: When a 1 is written into this bit, the operation specified in the EPC command field is performed at the specified EEPROM address.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet BITS DESCRIPTION TYPE DEFAULT 30-28 EPC command. This field is used to issue commands to the EEPROM controller. The EPC will execute commands when the EPC Busy bit is set. A new command must not be issued until the previous command completes.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet BITS 9 DESCRIPTION EPC Time-out. If an EEPROM operation is performed, and there is no response from the EEPROM within 30mS, the EEPROM controller will timeout and return to its idle state. This bit is set when a time-out occurs indicating that the last operation was unsuccessful.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.4 MAC Control and Status Registers These registers are located in the MAC module and are accessed indirectly through the MAC-CSR synchronizer port. Table 5.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.4.1 MAC_CR—MAC Control Register Offset: 1 Attribute: R/W Default Value: 00040000h Size: 32 bits This register establishes the RX and TX operation modes and controls for address filtering and packet filtering. BITS DESCRIPTION 31 Receive All Mode (RXALL).
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet BITS 13 DESCRIPTION Hash/Perfect Filtering Mode (HPFILT). When reset (0), the LAN9220 will implement a perfect address filter on incoming frames according the address specified in the MAC address register. When set (1), the address check Function does imperfect address filtering of multicast incoming frames according to the hash table specified in the multicast hash table register.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet BITS DESCRIPTION 7-6 BackOff Limit (BOLMT). The BOLMT bits allow the user to set its back-off limit in a relaxed or aggressive mode. According to IEEE 802.3, the MAC has to wait for a random number [r] of slottimes** after it detects a collision, where: (eq.1)0 < r < 2K The exponent K is dependent on how many times the current frame to be transmitted has been retried, as follows: (eq.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.4.2 ADDRH—MAC Address High Register Offset: 2 Attribute: R/W Default Value: 0000FFFFh Size: 32 bits The MAC Address High register contains the upper 16-bits of the physical address of the MAC. The contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM Controller if a programmed EEPROM is detected.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.4.3 ADDRL—MAC Address Low Register Offset: 3 Attribute: R/W Default Value: FFFFFFFFh Size: 32 bits The MAC Address Low register contains the lower 32 bits of the physical address of the MAC. The contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM Controller if a programmed EEPROM is detected.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Note: By convention, the left most byte of the Ethernet address (in this example 0x12) is the most significant byte and is transmitted/received first. 5.4.4 HASHH—Multicast Hash Table High Register Offset: 4 Attribute: R/W Default Value: 00000000h Size: 32 bits The 64-bit Multicast table is used for group address filtering.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.4.6 MII_ACC—MII Access Register Offset: 6 Attribute: R/W Default Value: 00000000h Size: 32 bits This register is used to control the Management cycles to the PHY. BITS DESCRIPTION 31-16 Reserved 15-11 PHY Address: For every access to this register, this field must be set to 00001b.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.4.8 FLOW—Flow Control Register Offset: 8 Attribute: R/W Default Value: 00000000h Size: 32 bits This register controls the generation and reception of the Control (Pause command) frames by the MAC’s flow control block. The control frame fields are selected as specified in the 802.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.4.9 VLAN1—VLAN1 Tag Register Offset: 9 Attribute: R/W Default Value: 00000000h Size: 32 bits This register contains the VLAN tag field to identify VLAN1 frames. For VLAN frames the legal frame length is increased from 1518 bytes to 1522 bytes. BITS DESCRIPTION 31-16 Reserved 15-0 VLAN1 Tag Identifier (VTI1). This contains the VLAN Tag field to identify the VLAN1 frames.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.4.11 WUFF—Wake-up Frame Filter Offset: B Attribute: WO Default Value: 00000000h Size: 32 bits This register is used to configure the wake up frame filter. BITS DESCRIPTION 31-0 Wake-Up Frame Filter (WFF). Wake-Up Frame Filter (WFF). The Wake-up frame filter is configured through this register using an indexing mechanism.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.4.13 COE_CR—Checksum Offload Engine Control Register Offset: D Attribute: R/W Default Value: 00000000h Size: 32 bits This register controls the transmit and receive checksum offload engines. BITS 31-17 16 DESCRIPTION Reserved TX Checksum Offload Engine Enable (TXCOE_EN). This bit enables/disables the Transmit COE. This bit may only be changed if the TX data path is disabled.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.5 PHY Registers The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC via the MII_ACC and MII_DATA registers. An index must be used to access individual PHY registers. PHY Register Indexes are shown in Table 5.8, "LAN9220 PHY Control and Status Register".
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.5.1 Basic Control Register Index (In Decimal): 0 Size: 16-bits BITS DESCRIPTION TYPE DEFAULT 15 Reset. 1 = software reset. Bit is self-clearing. For best results, when setting this bit do not set other bits in this register. RW/SC 0 14 Loopback. 1 = loopback mode, 0 = normal operation RW 0 13 Speed Select. 1 = 100Mbps, 0 = 10Mbps.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.5.2 Basic Status Register Index (In Decimal): BITS 1 Size: 16-bits DESCRIPTION TYPE DEFAULT 15 100Base-T4. 1 = T4 able, 0 = no T4 ability RO 0 14 100Base-TX Full Duplex. 1 = TX with full duplex, 0 = no TX full duplex ability. RO 1 13 100Base-TX Half Duplex. 1 = TX with half duplex, 0 = no TX half duplex ability. RO 1 12 10Base-T Full Duplex.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.5.4 PHY Identifier 2 Index (In Decimal): BITS 3 Size: 16-bits DESCRIPTION TYPE DEFAULT 0xC0C3h 15-10 PHY ID Number Assigned to the 19th through 24th bits of the OUI. RO 9-4 Model Number. Six-bit manufacturer’s model number. RO 3-0 Revision Number. Four-bit manufacturer’s revision number. RO 5.5.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.5.6 Auto-negotiation Link Partner Ability Index (In Decimal): BITS 5 Size: 16-bits DESCRIPTION TYPE DEFAULT 15 Next Page. 1 = next page capable, 0 = no next page ability. This device does not support next page ability. RO 0 14 Acknowledge.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.5.7 Auto-negotiation Expansion Index (In Decimal): BITS 15:5 6 Size: 16-bits DESCRIPTION Reserved TYPE DEFAULT RO 0 4 Parallel Detection Fault. 1 = fault detected by parallel detection logic 0 = no fault detected by parallel detection logic RO/LH 0 3 Link Partner Next Page Able.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.5.9 Special Modes Index (In Decimal): ADDRESS 18 Size: 16-bits DESCRIPTION TYPE DEFAULT 15-8 Reserved RW, NASR 7:5 MODE: PHY Mode of operation. Refer to Table 5.9 for more details. RW, NASR 111 4:0 PHYAD: PHY Address: The PHY Address is used for the SMI address. RW, NASR 00001b Table 5.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.5.10 Special Control/Status Indications Index (In Decimal): ADDRESS 27 Size: 16-bits DESCRIPTION MODE DEFAULT 15 Override AMDIX Strap 0 - AMDIX_EN (pin 52) enables or disables HP Auto MDIX 1 - Override pin 52. PHY Register 27.14 and 27.13 determine MDIX function RW 0 14 Auto-MDIX Enable: Only effective when 27.15=1, otherwise ignored. 0 = Disable Auto-MDIX. 27.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.5.11 Interrupt Source Flag Index (In Decimal): BITS 29 Size: 16-bits TYPE DEFAULT Reserved. Ignore on read. RO/LH 0 7 INT7. 1= ENERGYON generated, 0= not source of interrupt RO/LH 0 6 INT6. 1= Auto-Negotiation complete, 0= not source of interrupt RO/LH 0 5 INT5. 1= Remote Fault Detected, 0= not source of interrupt RO/LH 0 4 INT4.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 5.5.13 PHY Special Control/Status Index (In Decimal): BITS 31 Size: TYPE DEFAULT Reserved RO 000b Autodone. Auto-negotiation done indication: 0 = Auto-negotiation is not done or disabled (or not active) 1 = Auto-negotiation is done RO 0b 11-5 Reserved. Write as 0000010b, ignore on Read. RW 0000010b 4-2 Speed Indication.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Chapter 6 Timing Diagrams 6.1 Equivalent Test Load Output timing specifications assume an equivalent test load as illustrated in Figure 6.1 below. OUTPUT Test load varies dependent on VDDVARIO: VDDVARIO = 3.3V ± 300mV: 25pF VDDVARIO = 2.5V ± 10%: 10pF VDDVARIO=1.8V ± 10%: 10pF Figure 6.1 Equivalent Test Load 6.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 6.2.1 Special Restrictions on Back-to-Back Write/Read Cycles It is important to note that there are specific restrictions on the timing of back-to-back write-read operations. These restrictions concern reading the control registers after any write cycle to the LAN9220 device.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 6.1 Read After Write Timing Rules (continued) REGISTER NAME MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) NUMBER OF BYTE_TEST READS (ASSUMING TCYCLE OF 165NS) RX_DROP 0 0 MAC_CSR_CMD 165 1 MAC_CSR_DATA 165 1 AFC_CFG 165 1 E2P_CMD 165 1 E2P_DATA 165 1 6.2.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 6.3 PIO Reads PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between cycles for the period specified.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. Parameters tcsh and tcsl must be extended using wait states to meet the tcycle minimum. 6.4 PIO Burst Reads In this mode, performance is improved by allowing up to 16 WORD read cycles back-to-back.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 6.5 RX Data FIFO Direct PIO Reads In this mode the upper address inputs are not decoded, and any read of the LAN9220 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to high-order address line.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 6.6 RX Data FIFO Direct PIO Burst Reads In this mode the upper address inputs are not decoded, and any burst read of the LAN9220 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 6.7 PIO Writes PIO writes are used for all LAN9220 write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). Either or both of these control signals must go high between cycles for the period specified. A[7:1] nCS, nWR Data Bus Figure 6.6 PIO Write Cycle Timing Note: The “Data Bus” width is 16 bits. Table 6.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 6.8 TX Data FIFO Direct PIO Writes In this mode the upper address inputs are not decoded, and any write to the LAN9220 will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 6.9 Power Sequence Timing Figure 6.8 illustrates the device’s power sequencing requirements. Device power supplies can turn on in any order provided they all reach operational levels within the specified time period tpon. Device power supplies can turn off in any order provided they all reach 0 volts within the specified time period tpoff. tpon tpoff VDDVARIO 3.3V (All) Figure 6.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 6.10 Reset Timing T6.1 nRESET T6.2 T6.3 Configuration signals T6.4 Output drive Figure 6.9 Reset Timing Table 6.10 Reset Timing PARAMETER DESCRIPTION MIN TYP MAX UNITS T6.1 Reset Pulse Width 30 ms T6.2 Configuration input setup to nRESET rising 200 ns T6.3 Configuration input hold after nRESET rising 10 ns T6.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 6.11 EEPROM Timing The following specifies the EEPROM timing requirements for the LAN9220: Figure 6.10 EEPROM Timing Table 6.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Chapter 7 Operational Characteristics 7.1 Absolute Maximum Ratings* Supply Voltage (VDDVARIO, VDD33REG, VDD33A) (Note 7.1) . . . . . . . . . . . . . . . . . . . . . 0V to +3.6V Positive voltage on signal pins, with respect to ground (Note 7.2) . . . . . . . . . . . . . . . . . . . . . . . . . . +6V Negative voltage on signal pins, with respect to ground (Note 7.3) . . . . . . . . . . . .
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 7.3 Power Consumption (Device Only) This section provides typical power consumption values for the LAN9220 in various modes of operation. These measurements were taken under the following conditions: Temperature: ...................................................................................................................................
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 7.4 Power Consumption (Device and System Components) This section provides typical power consumption values for a complete Ethernet interface based on the LAN9220, including the power dissipated by the magnetics and other passive components. Note: The power measurements list below were taken under the following conditions: Temperature: ...................................................
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 7.5 Worst Case Current Consumption This section details the worst case current consumption for each device power supply. These values are provided to assist system designers with proper power supply design. These values cannot be used to determine typical power consumption of the device.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 7.6 DC Electrical Specifications This section details the DC electrical specifications of the LAN9220 I/O buffers. The electrical specifications in this section are valid over the indicated voltage range and the temperature range specified in Section 7.2, "Operating Conditions**". Note: When operating at reduced VDDVARIO voltage levels (less than 3.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 7.7 I/O Buffer Characteristics VDDVARIO=2.5V +/- 10% PARAMETER SYMBOL MIN Low Input Level VILI -0.3 High Input Level VIHI Negative-Going Threshold VILT 0.78 Positive-Going Threshold VIHT Schmitt Trigger Hysteresis (VIHT - VILT) TYP MAX UNITS NOTES VIS Type Input Buffer V 5.5 V 0.94 1.1 V Schmitt Trigger 1.13 1.32 1.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 7.8 I/O Buffer Characteristics VDDVARIO=1.8V +/- 10% PARAMETER SYMBOL MIN Low Input Level VILI -0.3 High Input Level VIHI Negative-Going Threshold VILT 0.54 Positive-Going Threshold VIHT Schmitt Trigger Hysteresis (VIHT - VILT) TYP MAX UNITS NOTES VIS Type Input Buffer V 5.25 V 0.69 0.83 V Schmitt Trigger 0.878 1.06 1.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 7.9 100BASE-TX Transceiver Characteristics PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Peak Differential Output Voltage High VPPH 950 - 1050 mVpk Note 7.8 Peak Differential Output Voltage Low VPPL -950 - -1050 mVpk Note 7.8 Signal Amplitude Symmetry VSS 98 - 102 % Note 7.8 Signal Rise & Fall Time TRF 3.0 - 5.0 nS Note 7.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet 7.7 Clock Circuit The LAN9220 can accept either a 25MHz crystal (preferred) or a 25 MHz single-ended clock oscillator (±50 PPM) input. The LAN9220 shares the 25MHz clock oscillator input (CLKIN) with the crystal input XTAL1/CLKIN. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and CLKIN should be driven with a nominal 0-3.3V clock signal.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Chapter 8 Package Outline 8.1 56-QFN Package Figure 8.1 56 Pin QFN Package Definition Table 8.1 56 Pin QFN Package Parameters A A1 A2 D/E D1/E1 D2/E2 L b e MIN 0.70 0.00 ~ 7.85 7.55 5.75 0.30 0.18 NOMINAL ~ 0.02 ~ 8.00 ~ 5.90 ~ 0.25 0.50 Basic MAX 1.00 0.05 0.90 8.15 7.95 6.05 0.50 0.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Figure 8.2 56 Pin QFN Recommended PCB Land Pattern SMSC LAN9220 149 DATASHEET Revision 2.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Chapter 9 Datasheet Revision History Table 9.1 Customer Revision History REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION Rev. 2.9 (03-01-12) Section 5.4.8, "FLOW—Flow Control Register," on page 113 Updated Pass Control Frames (bit 2) description to “When set, the MAC will pass the pause frame to the host...” Rev. 2.8 (07-14-11) Table 2.
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16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support Datasheet Table 9.1 Customer Revision History (continued) REVISION LEVEL & DATE Rev. 2.3 (08-18-08) SECTION/FIGURE/ENTRY Note 7.7 on page 145 CORRECTION Note following I/O Buffer Characteristics table modified: Changed from: ".....the per-pin input leakage is 10 divided by the maximum input leakage current." to: ".....the per-pin input leakage is the maximum input leakage current divided by 10.