Datasheet

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 2011-2014 Microchip Technology Inc. DS70000652F-page 193

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104

(1,2,3,4)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L

bit 15 bit 8

R/W-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1

FLTBM

— — — — FBEN3 FBEN2 FBEN1

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13-8 FBOV<3:1>H:FBOV<3:1>L: Fault Input B PWMx Override Value bits

1 = The PWMx output pin is driven active on an external Fault input event

0 = The PWMx output pin is driven inactive on an external Fault input event

bit 7 FLTBM: Fault B Mode bit

1 = The Fault B input pin functions in the Cycle-by-Cycle mode

0 = The Fault B input pin latches all control pins to the programmed states in PxFLTBCON<13:8>

bit 6-3 Unimplemented: Read as ‘0’

bit 2 FBEN3: Fault Input B Enable bit

1 = PWMxH3/PWMxL3 pin pair is controlled by Fault Input B

0 = PWMxH3/PWMxL3 pin pair is not controlled by Fault Input B

bit 1 FBEN2: Fault Input B Enable bit

1 = PWMxH2/PWMxL2 pin pair is controlled by Fault Input B

0 = PWMxH2/PWMxL2 pin pair is not controlled by Fault Input B

bit 0 FBEN1: Fault Input B Enable bit

1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input B

0 = PWMxH1/PWMxL1 pin pair is not controlled by Fault Input B

Note 1: Comparator outputs are not internally connected to the PWM Fault control logic. If using the comparator

modules for Fault generation, the user must externally connect the desired comparator output pin to the

dedicated FLTA1

or FLTB1 input pin.

2: Refer to Table 15-1 for FLTB1 implementation details.

3: The PxFLTACON register is a write-protected register. Refer to Section 15.3 “Write-Protected Registers”

for more information on the unlock sequence.

4: During any Reset event, FLTB1

is enabled by default and must be cleared as described in Section 15.2

“PWM Faults”.