Datasheet

 2011-2014 Microchip Technology Inc. DS70000652F-page 57
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0020
MODCON 0046 XMODEN YMODEN
— — BWM3 BWM2 BWM1 BWM0 YWM3 YWM2 YWM1 YWM0 XWM3 XWM2 XWM1 XWM0 0000
XMODSRT 0048 XS<15:1> 0 xxxx
XMODEND 004A XE<15:1> 1 xxxx
YMODSRT 004C YS<15:1> 0 xxxx
YMODEND 004E YE<15:1> 1 xxxx
XBREV 0050 BREN XB<14:0> xxxx
DISICNT 0052
— — Disable Interrupts Counter Register 0000
TABLE 4-1: CPU CORE REGISTER MAP (CONTINUED)
SFR Name
SFR
Addr
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.