Datasheet
Table Of Contents
- Features
- CMOS Technology
- Packages
- Package Types
- Block Diagram
- 1.0 Device OvervieW
- 1.1 Pin Descriptions
- 1.2 Power-on Reset (POR)
- 1.3 Power-up Timer (PWRT)
- 1.4 Clock Generator
- 1.5 I2C Bus Interface/ Protocol Handler
- 1.6 Address Decoder
- 1.7 Register Block
- 1.8 Serializer/Deserializer
- 1.9 Interrupt Logic
- 2.0 Electrical Characteristics
- 2.1 DC Characteristics
- TABLE 2-1: DC Characteristics
- FIGURE 2-1: respOnse time
- TABLE 2-2: response time
- FIGURE 2-2: TEST POINT Clock Timing
- TABLE 2-3: TEST POINT Clock Timing
- TABLE 2-4: Power-up Timer Requirements
- FIGURE 2-3: I2C Bus Start/Stop Bits Timing
- FIGURE 2-4: I2C Bus Data Timing
- TABLE 2-5: I2C Bus Data Requirements
- FIGURE 2-5: GP0 and GP1 POrt Timings
- 2.1 DC Characteristics
- 3.0 Package InFormation
- Appendix A: Revision History
- Product Identification System
- Worldwide Sales and Service
MCP23016
DS20090C-page 14 © 2007 Microchip Technology Inc.
FIGURE 1-4: WRITE TO CONFIGURATION
REGISTERS (CASE 2)
FIGURE 1-5: WRITE TO OUTPUT PORTS
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 0 A2 A1 A0
D0
S
0
R/W
=0
ACK
D6 D5 D4 D3 D2 D1
D7
ACK
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
D0 D6 D5 D4 D3 D2 D1
D7 ACK
D0 D6 D5 D4 D3 D2 D1
D7 ACK
Address
Command Byte
Data 1
Data 2
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
D0 D6 D5 D4 D3 D2 D1
D7
ACK
D0 D6 D5 D4 D3 D2 D1
D7
ACK
P
Data 1
Data 2
SCL held low until
data is processed
SCL held low until
data is processed
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 0 A2 A1 A0 D0
S
0
R/W
=0
ACK D6 D5 D4 D3 D2 D1D7
ACK
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
D0D6 D5 D4 D3 D2 D1D7
ACK
D0D6 D5 D4 D3 D2 D1D7
ACK
P
Address
Command Byte Data 1
Data 2
DATA VALID
t
GPV0
DATA
VALID
t
GPV1
SDA
SCL
Data on GP0
Data on GP1
SCL held low until
data is processed